53 Publikationen

Alle markieren

[53]
2019 | Sammelwerksbeitrag | Veröffentlicht | PUB-ID: 2920469
Oleksiak A, Kierzynka M, Porrmann M, et al. M2DC – A Novel Heterogeneous Hyperscale Microserver Platform. In: Kachris C, Falsafi B, Soudris D, eds. Hardware Accelerators in Data Centers. 1st ed. Cham, Switzerland: Springer International Publishing AG; 2019: 109-128.
PUB | DOI
 
[52]
2018 | Zeitschriftenaufsatz | E-Veröff. vor dem Druck | PUB-ID: 2920468
Ibraheem OW, Irwansyah A, Hagemeyer J, Porrmann M, Rückert U. FPGA-Based Vision Processing System for Automatic Online Player Tracking in Indoor Sports. Journal of Signal Processing Systems. 2018.
PUB | DOI | WoS
 
[51]
2018 | Konferenzbeitrag | PUB-ID: 2921314
Klimeck D, Meyer HG, Hagemeyer J, Porrmann M, Rückert U. Resource-efficient Reconfigurable Computer-on-Module for Embedded Vision Applications. Presented at the 29th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2018), Milan, Italy.
PUB
 
[50]
2018 | Kurzbeitrag Konferenz / Poster | Veröffentlicht | PUB-ID: 2918788 OA
Kaiser M, Pilz S, Porrmann F, Hagemeyer J, Porrmann M. Accelerating Hamming Distance Comparisons for Locality Sensitive Hashing (LSH) using FPGAs. In: 12th CeBiTec Symposium - Big Data in Medicine and Biotechnology - Abstract Book. Vol 12. Bielefeld; 2018: 48-49.
PUB | PDF
 
[49]
2017 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2937407
Agosta G, Barenghi A, Ciesielczyk T, et al. The M2DC Approach towards Resource-efficient Computing. In: Bagnato A, Couceiro R, Monteiro J, Petrovska-Delacrétaz D, Lopes A, Gouveia É, eds. OPPORTUNITIES AND CHALLENGES for European Projects. Volume 1: EPS Portugal 2017/2018. Setúbal, Portugal: SCITEPRESS; 2017: 150-176.
PUB | DOI
 
[48]
2017 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2912818
Oleksiak A, Kierzynka M, Piatek W, et al. M2DC – Modular Microserver DataCentre with heterogeneous hardware. Microprocessors and Microsystems. 2017;52:117-130.
PUB | DOI | WoS
 
[47]
2017 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2912815
Ibraheem OW, Irwansyah A, Hagemeyer J, Porrmann M, Rückert U. Reconfigurable Vision Processing System for Player Tracking in Indoor Sports. In: Conference on Design and Architectures for Signal and Image Processing (DASIP 2017). Piscataway, NJ: IEEE; 2017: 1-6.
PUB | DOI
 
[46]
2017 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2909430
Irwansyah A, Ibraheem OW, Hagemeyer J, Porrmann M, Rückert U. FPGA-based Multi-Robot Tracking. Journal of Parallel and Distributed Computing. 2017;107:146-161.
PUB | DOI | Download (ext.) | WoS
 
[45]
2017 | Kurzbeitrag Konferenz / Poster | Veröffentlicht | PUB-ID: 2918683 OA
Kaiser M, Griessl R, Hagemeyer J, et al. A Reconfigurable Heterogeneous Microserver Architecture for Energy-efficient Computing. In: Third International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC'17). Denver, CO; 2017.
PUB | PDF | Download (ext.)
 
[44]
2017 | Konferenzbeitrag | PUB-ID: 2909584
Oleksiak A, Kierzynka M, Piatek W, et al. M2DC: Modular Microserver Datacentre with Heterogeneous Hardware. Presented at the Energy-efficient Servers for Cloud and Edge Computing 2017 Workshop (ENeSCE 2017) - co-located with HiPEAC 2017, Stockholm, Sweden.
PUB
 
[43]
2017 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2915029
Tlatlik J, Hansen T, Lachmair J, Hagemeyer J. Entwurf eines FPGA-basierten Verbindungsknotens als Prototypenumgebung für energieeffiziente und sichere Gebäudeautomationssysteme. In: Schulze S-O, Tschirner C, Kaffenberger R, Ackva S, eds. Tag des Systems Engineering: Paderborn, 8. -10. November 2017. München: Carl Hanser Verlag GmbH Co KG; 2017: 55-- 64.
PUB
 
[42]
2017 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2909044
Lachmair J, Mieth T, Griessl R, Hagemeyer J, Porrmann M. From CPU to FPGA – Acceleration of Self-Organizing Maps for Data Mining. In: International Joint Conference on Neural Networks (IJCNN 2017). 2017: 4299-4308.
PUB
 
[41]
2016 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2908973
Cozzi D, Korf S, Cassano L, et al. OLT(RE)²: an On-Line on-demand Testing approach for permanent Radiation Effects in REconfigurable systems. IEEE Transactions on Emerging Topics in Computing. 2016;PP(99):1-1.
PUB | DOI | WoS
 
[40]
2016 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2908974
Oleksiak A, Porrmann M, Hagemeyer J, et al. Data centres for IoT applications: The M2DC approach (Invited paper). In: 2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS). 2016: 293-299.
PUB | DOI
 
[39]
2016 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2903257 OA
Kierzynka M, Kosmann L, vor dem Berge M, et al. Energy Efficiency of Sequence Alignment Tools - Software and Hardware Perspectives. Future Generation Computer Systems. 2016;67:455-465.
PUB | PDF | DOI | Download (ext.) | WoS
 
[38]
2016 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2908980
Cecowski M, Agosta G, Oleksiak A, et al. The M2DC Project: Modular Microserver DataCentre. In: 2016 Euromicro Conference on Digital System Design (DSD). Institute of Electrical and Electronics Engineers (IEEE); 2016.
PUB | DOI
 
[37]
2016 | Kurzbeitrag Konferenz / Poster | PUB-ID: 2909602 OA
Griessl R, Peykanu M, Tigges L, Hagemeyer J, Porrmann M. FiPS and M2DC: Novel Architectures for Reconfigurable Hyperscale Servers. Presented at the Workshop "Reconfigurable Computing — From Embedded Systems to Reconfigurable Hyperscale Servers" co-located with the International Conference on Field-Programmable Logic and Applications (FPL 2016), Lausanne, Switzerland.
PUB | Download (ext.)
 
[36]
2015 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2901108
Irwansyah A, Ibraheem OW, Hagemeyer J, Porrmann M, Rückert U. FPGA-based circular hough transform with graph clustering for vision-based multi-robot tracking. In: ReConFigurable Computing and FPGAs (ReConFig), 2015 International Conference on. IEEE; 2015: 1-8.
PUB | DOI
 
[35]
2015 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2901107
Ibraheem OW, Irwansyah A, Hagemeyer J, Porrmann M, Rückert U. A resource-efficient multi-camera GigE vision IP core for embedded vision processing platforms. In: ReConFigurable Computing and FPGAs (ReConFig), 2015 International Conference on. IEEE; 2015: 1-6.
PUB | DOI
 
[34]
2015 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2902039 OA
Griessl R, Peykanu M, Hagemeyer J, et al. FPGA-accelerated Heterogeneous Hyperscale Server Architecture for Next-Generation Compute Clusters. Presented at the First International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC‘15), held in conjunction with Supercomputing 2015, Austin Texas, USA.
PUB | PDF
 
[33]
2014 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2681323
Sabena D, Sterpone L, Schölzel M, et al. Reconfigurable High Performance Architectures: How much are they ready for safety-critical applications. In: Proceedings of 19th IEEE European Test Symposium (ETS). 2014: 175-182.
PUB | DOI | Download (ext.)
 
[32]
2014 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2698999
Sorrenti D, Cozzi D, Korf S, et al. Exploiting Dynamic Partial Reconfiguration for On-Line On-Demand Testing of Permanent Faults in Reconfigurable Systems. Presented at the 17th IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Amsterdam, The Netherlands.
PUB | DOI | Download (ext.)
 
[31]
2014 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2699005
Cozzi D, Jungewelter D, Kleibrink D, et al. AXI-based SpaceFibre IP CORE Implementation. Presented at the 6th International SpaceWire Conference, Athens, Greece.
PUB | DOI | Download (ext.)
 
[30]
2014 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2698930
Griessl R, Peykanu M, Hagemeyer J, et al. A Scalable Server Architecture for Next-Generation Heterogeneous Compute Clusters. In: Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, EUC 2014. IEEE; 2014: 146-153.
PUB | DOI | Download (ext.)
 
[29]
2014 | Konferenzbeitrag | PUB-ID: 2681362
Cassano L, Cozzi D, Jungewelter D, et al. An Inter-Processor Communication Interface for Data-Flow Centric Heterogeneous Embedded Multiprocessor Systems. Presented at the DTIS 2014, 9th International conference on Design & Technology of Integrated Systems in Nanoscale Era, Santorini , Greece.
PUB | DOI | Download (ext.)
 
[28]
2013 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2576115 OA
Korf S, Sievers G, Ax J, et al. Dynamisch rekonfigurierbare Hardware als Basistechnologie für intelligente technische Systeme. In: Proceedings Wissenschaftsforum 2013 Intelligente Technische Systeme. HNI-Verlagsschriftenreihe. 2013: 79-90.
PUB | PDF
 
[27]
2013 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2622226
Sterpone L, Porrmann M, Hagemeyer J. A Novel Fault Tolerant and Runtime Reconfigurable Platform for Satellite Payload Processing. IEEE Transactions on Computers. 2013;62(8):1508-1525.
PUB | DOI | WoS
 
[26]
2013 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2681289
Desogus M, Sterpone L, Porrmann M, Hagemeyer J, Illstad J. Hardening Dynamically Reconfigurable Processing Modules Architectures: A Neutron Test Experience. In: RADECS proceedings. Vol 2. IEEE / Institute of Electrical and Electronics Engineers; 2013: 13-16.
PUB
 
[25]
2013 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2681304
Sterpone L, Sabena D, Ullah A, Porrmann M, Hagemeyer J, Ilstad J. Dynamic neutron testing of Dynamically Reconfigurable Processing Modules architecture. In: Adaptive Hardware and Systems (AHS), 2013 NASA/ESA Conference on. 2013: 184-188.
PUB | DOI | Download (ext.)
 
[24]
2013 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2576042
Cassano L, Cozzi D, Korf S, Hagemeyer J, Porrmann M, Sterpone L. On-Line Testing of Permanent Radiation Effects in Reconfigurable Systems. In: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013. Piscataway, NJ: IEEE; 2013: 717-720.
PUB | DOI
 
[23]
2012 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2559365
Romoth J, Jungewelter D, Hagemeyer J, Porrmann M, Rückert U. Optimizing inter-FPGA communication by automatic channel adaptation. In: Reconfigurable Computing and FPGAs (ReConFig), 2012 International Conference on. 2012: 1-7.
PUB | DOI
 
[22]
2012 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2517354
Hagemeyer J, Hilgenstein A, Jungewelter D, et al. A Scalable Platform for Run-time Reconfigurable Satellite Payload Processing. In: 2012 NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2012). Piscataway, NJ: IEEE; 2012: 9-16.
PUB | DOI | Download (ext.)
 
[21]
2011 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493823
Grawinkel M, Schäfers T, Brinkmann A, Hagemeyer J, Porrmann M. Evaluation of Applied Intra-Disk Redundancy Schemes to Improve Single Disk Reliability. In: MASCOTS2011 The 19th Annual Meeting of the IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems. 2011: 297-306.
PUB | DOI | Download (ext.)
 
[20]
2011 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493819
Sterpone L, Margaglia F, Köster M, Hagemeyer J, Porrmann M. Analysis of SEU Effects in Partially Reconfigurable SoPCs. In: Proceedings of NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2011). 2011: 129-136.
PUB | DOI
 
[19]
2011 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494507
Romoth J, Hagemeyer J, Porrmann M, Rückert U. Fast Design-space Exploration with FPGA Cluster. In: DATE 2011 Workshop on Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing. 2011.
PUB | Download (ext.)
 
[18]
2011 | Kurzbeitrag Konferenz / Poster | Veröffentlicht | PUB-ID: 2494497
Köster M, Hagemeyer J, Margaglia F, et al. Design Flow for a Fault-Tolerant Reconfigurable Multi-FPGA Architecture for Space Applications. In: DATE 2011 Workshop on Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing. 2011.
PUB
 
[17]
2011 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286173
Korf S, Cozzi D, Koester M, et al. Automatic HDL-Based Generation of Homogeneous Hard Macros for FPGAs. In: Field-Programmable Custom Computing Machines (FCCM), 2011 IEEE 19th Annual International Symposium on. 2011: 125-132.
PUB | Download (ext.)
 
[16]
2010 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493826
Dittmann F, Linke M, Hagemeyer J, et al. Implementation of a Dynamically Reconfigurable Processing Module for SpaceWire Networks. In: Proceedings of the International SpaceWire Conference 2010. 2010: 193-196.
PUB | Download (ext.)
 
[15]
2010 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472693 OA
Porrmann M, Hagemeyer J, Pohl C, Romoth J, Strugholtz M. RAPTOR – A Scalable Platform for Rapid Prototyping and FPGA-based Cluster Computing. In: Parallel Computing: From Multicores and GPU's to Petascale, Advances in Parallel Computing. Vol 19. IOS press; 2010: 592-599.
PUB | PDF
 
[14]
2010 | Patent | Veröffentlicht | PUB-ID: 2494087
Christmann W, Strugholtz M, Hagemeyer J, Porrmann M. Mehrprozessor-Computersystem. 2010.
PUB
 
[13]
2010 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2145423
Koester M, Luk W, Hagemeyer J, Porrmann M, Rückert U. Design Optimizations for Tiled Partially Reconfigurable Systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2010;19(6):1048-1061.
PUB | DOI | WoS
 
[12]
2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472673
Koester M, Luk W, Hagemeyer J, Porrmann M. Design Optimizations to Improve Placeability of Partial Reconfiguration Modules. In: Proceedings of the International Conference on Design, Automation and Test in Europe (DATE 2009). ACM Press; 2009.
PUB | DOI | Download (ext.)
 
[11]
2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472678
Porrmann M, Hagemeyer J, Romoth J, Strugholtz M. Rapid Prototyping of Next-Generation Multiprocessor SoCs. In: Proceedings of Semiconductor Conference Dresden, SCD 2009. Dresden, Germany; 2009.
PUB
 
[10]
2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472686
Grassi PR, Santambrogio M, Hagemeyer J, Pohl C, Porrmann M. SiLLis: A Simplified Language for Monitoring and Debugging of Reconfigurable Systems. In: Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '09). Las Vegas, USA; 2009: 174-180.
PUB
 
[9]
2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2144891
Paiz C, Pohl C, Radkowski R, Hagemeyer J, Porrmann M, Rückert U. FPGA-in-the-Loop-Simulations for Dynamically Reconfigurable Applications. In: Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT'09). The University of New South Wales, Sydney, Australia, 9-11, Sydney, Australia; 2009: 372-375.
PUB | DOI
 
[8]
2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2144880
Pohl C, Hagemeyer J, Porrmann M, Rückert U. Using a Reconfigurable Compute Cluster for the Acceleration of Neural Networks. In: Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT '09). Sydney, Australia; 2009: 368-371.
PUB | DOI
 
[7]
2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2144843 OA
Paiz C, Hagemeyer J, Pohl C, et al. FPGA-Based Realization of Self-Optimizing Drive-Controllers. In: the 35th Annual Conference of the IEEE Industrial Electronics Society (IECON 2009). 2009: 2868-2873.
PUB | PDF | DOI | Download (ext.)
 
[6]
2008 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472725
Hagemeyer J, Koester M, Porrmann M. Hardware Virtualization Exploiting Dynamically Reconfigurable Architectures. In: 1. GI/ITG KuVS Fachgespräch Virtualisierung. Heinz Nixdorf Institut, Universität Paderborn; 2008.
PUB
 
[5]
2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472738
Hagemeyer J, Kettelhoit B, Koester M, Porrmann M. Design of Homogeneous Communication Infrastructures for Partially Reconfigurable FPGAs. In: Proc. of the Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA '07). Las Vegas, USA; 2007.
PUB | Download (ext.)
 
[4]
2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472729
Schulz B, Paiz C, Hagemeyer J, Mathapati S, Porrmann M, Böcker J. Run-Time Reconfiguration of FPGA-Based Drive Controllers. In: European Conference on Power Electronics and Applications (EPE 2007). Aalborg, Denmark; 2007.
PUB | DOI
 
[3]
2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472743
Hagemeyer J, Kettelhoit B, Koester M, Porrmann M. A Design Methodology for Communication Infrastructures on Partially Reconfigurable FPGAS. In: Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL). Amsterdam, Netherlands; 2007: 331-338.
PUB | DOI
 
[2]
2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472748
Hagemeyer J, Kettelhoit B, Koester M, Porrmann M. INDRA – Integrated Design Flow for Reconfigurable Architectures. In: Proceedings of the Conference on Design, Automation and Test in Europe (DATE '07) – University Booth. 2007.
PUB | Download (ext.)
 
[1]
2006 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2473942
Hagemeyer J, Kettelhoit B, Porrmann M. Dedicated Module Access in Dynamically Reconfigurable Systems. In: Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS). 2006.
PUB | DOI
 

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53 Publikationen

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[53]
2019 | Sammelwerksbeitrag | Veröffentlicht | PUB-ID: 2920469
Oleksiak A, Kierzynka M, Porrmann M, et al. M2DC – A Novel Heterogeneous Hyperscale Microserver Platform. In: Kachris C, Falsafi B, Soudris D, eds. Hardware Accelerators in Data Centers. 1st ed. Cham, Switzerland: Springer International Publishing AG; 2019: 109-128.
PUB | DOI
 
[52]
2018 | Zeitschriftenaufsatz | E-Veröff. vor dem Druck | PUB-ID: 2920468
Ibraheem OW, Irwansyah A, Hagemeyer J, Porrmann M, Rückert U. FPGA-Based Vision Processing System for Automatic Online Player Tracking in Indoor Sports. Journal of Signal Processing Systems. 2018.
PUB | DOI | WoS
 
[51]
2018 | Konferenzbeitrag | PUB-ID: 2921314
Klimeck D, Meyer HG, Hagemeyer J, Porrmann M, Rückert U. Resource-efficient Reconfigurable Computer-on-Module for Embedded Vision Applications. Presented at the 29th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2018), Milan, Italy.
PUB
 
[50]
2018 | Kurzbeitrag Konferenz / Poster | Veröffentlicht | PUB-ID: 2918788 OA
Kaiser M, Pilz S, Porrmann F, Hagemeyer J, Porrmann M. Accelerating Hamming Distance Comparisons for Locality Sensitive Hashing (LSH) using FPGAs. In: 12th CeBiTec Symposium - Big Data in Medicine and Biotechnology - Abstract Book. Vol 12. Bielefeld; 2018: 48-49.
PUB | PDF
 
[49]
2017 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2937407
Agosta G, Barenghi A, Ciesielczyk T, et al. The M2DC Approach towards Resource-efficient Computing. In: Bagnato A, Couceiro R, Monteiro J, Petrovska-Delacrétaz D, Lopes A, Gouveia É, eds. OPPORTUNITIES AND CHALLENGES for European Projects. Volume 1: EPS Portugal 2017/2018. Setúbal, Portugal: SCITEPRESS; 2017: 150-176.
PUB | DOI
 
[48]
2017 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2912818
Oleksiak A, Kierzynka M, Piatek W, et al. M2DC – Modular Microserver DataCentre with heterogeneous hardware. Microprocessors and Microsystems. 2017;52:117-130.
PUB | DOI | WoS
 
[47]
2017 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2912815
Ibraheem OW, Irwansyah A, Hagemeyer J, Porrmann M, Rückert U. Reconfigurable Vision Processing System for Player Tracking in Indoor Sports. In: Conference on Design and Architectures for Signal and Image Processing (DASIP 2017). Piscataway, NJ: IEEE; 2017: 1-6.
PUB | DOI
 
[46]
2017 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2909430
Irwansyah A, Ibraheem OW, Hagemeyer J, Porrmann M, Rückert U. FPGA-based Multi-Robot Tracking. Journal of Parallel and Distributed Computing. 2017;107:146-161.
PUB | DOI | Download (ext.) | WoS
 
[45]
2017 | Kurzbeitrag Konferenz / Poster | Veröffentlicht | PUB-ID: 2918683 OA
Kaiser M, Griessl R, Hagemeyer J, et al. A Reconfigurable Heterogeneous Microserver Architecture for Energy-efficient Computing. In: Third International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC'17). Denver, CO; 2017.
PUB | PDF | Download (ext.)
 
[44]
2017 | Konferenzbeitrag | PUB-ID: 2909584
Oleksiak A, Kierzynka M, Piatek W, et al. M2DC: Modular Microserver Datacentre with Heterogeneous Hardware. Presented at the Energy-efficient Servers for Cloud and Edge Computing 2017 Workshop (ENeSCE 2017) - co-located with HiPEAC 2017, Stockholm, Sweden.
PUB
 
[43]
2017 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2915029
Tlatlik J, Hansen T, Lachmair J, Hagemeyer J. Entwurf eines FPGA-basierten Verbindungsknotens als Prototypenumgebung für energieeffiziente und sichere Gebäudeautomationssysteme. In: Schulze S-O, Tschirner C, Kaffenberger R, Ackva S, eds. Tag des Systems Engineering: Paderborn, 8. -10. November 2017. München: Carl Hanser Verlag GmbH Co KG; 2017: 55-- 64.
PUB
 
[42]
2017 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2909044
Lachmair J, Mieth T, Griessl R, Hagemeyer J, Porrmann M. From CPU to FPGA – Acceleration of Self-Organizing Maps for Data Mining. In: International Joint Conference on Neural Networks (IJCNN 2017). 2017: 4299-4308.
PUB
 
[41]
2016 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2908973
Cozzi D, Korf S, Cassano L, et al. OLT(RE)²: an On-Line on-demand Testing approach for permanent Radiation Effects in REconfigurable systems. IEEE Transactions on Emerging Topics in Computing. 2016;PP(99):1-1.
PUB | DOI | WoS
 
[40]
2016 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2908974
Oleksiak A, Porrmann M, Hagemeyer J, et al. Data centres for IoT applications: The M2DC approach (Invited paper). In: 2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS). 2016: 293-299.
PUB | DOI
 
[39]
2016 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2903257 OA
Kierzynka M, Kosmann L, vor dem Berge M, et al. Energy Efficiency of Sequence Alignment Tools - Software and Hardware Perspectives. Future Generation Computer Systems. 2016;67:455-465.
PUB | PDF | DOI | Download (ext.) | WoS
 
[38]
2016 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2908980
Cecowski M, Agosta G, Oleksiak A, et al. The M2DC Project: Modular Microserver DataCentre. In: 2016 Euromicro Conference on Digital System Design (DSD). Institute of Electrical and Electronics Engineers (IEEE); 2016.
PUB | DOI
 
[37]
2016 | Kurzbeitrag Konferenz / Poster | PUB-ID: 2909602 OA
Griessl R, Peykanu M, Tigges L, Hagemeyer J, Porrmann M. FiPS and M2DC: Novel Architectures for Reconfigurable Hyperscale Servers. Presented at the Workshop "Reconfigurable Computing — From Embedded Systems to Reconfigurable Hyperscale Servers" co-located with the International Conference on Field-Programmable Logic and Applications (FPL 2016), Lausanne, Switzerland.
PUB | Download (ext.)
 
[36]
2015 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2901108
Irwansyah A, Ibraheem OW, Hagemeyer J, Porrmann M, Rückert U. FPGA-based circular hough transform with graph clustering for vision-based multi-robot tracking. In: ReConFigurable Computing and FPGAs (ReConFig), 2015 International Conference on. IEEE; 2015: 1-8.
PUB | DOI
 
[35]
2015 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2901107
Ibraheem OW, Irwansyah A, Hagemeyer J, Porrmann M, Rückert U. A resource-efficient multi-camera GigE vision IP core for embedded vision processing platforms. In: ReConFigurable Computing and FPGAs (ReConFig), 2015 International Conference on. IEEE; 2015: 1-6.
PUB | DOI
 
[34]
2015 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2902039 OA
Griessl R, Peykanu M, Hagemeyer J, et al. FPGA-accelerated Heterogeneous Hyperscale Server Architecture for Next-Generation Compute Clusters. Presented at the First International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC‘15), held in conjunction with Supercomputing 2015, Austin Texas, USA.
PUB | PDF
 
[33]
2014 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2681323
Sabena D, Sterpone L, Schölzel M, et al. Reconfigurable High Performance Architectures: How much are they ready for safety-critical applications. In: Proceedings of 19th IEEE European Test Symposium (ETS). 2014: 175-182.
PUB | DOI | Download (ext.)
 
[32]
2014 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2698999
Sorrenti D, Cozzi D, Korf S, et al. Exploiting Dynamic Partial Reconfiguration for On-Line On-Demand Testing of Permanent Faults in Reconfigurable Systems. Presented at the 17th IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Amsterdam, The Netherlands.
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[31]
2014 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2699005
Cozzi D, Jungewelter D, Kleibrink D, et al. AXI-based SpaceFibre IP CORE Implementation. Presented at the 6th International SpaceWire Conference, Athens, Greece.
PUB | DOI | Download (ext.)
 
[30]
2014 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2698930
Griessl R, Peykanu M, Hagemeyer J, et al. A Scalable Server Architecture for Next-Generation Heterogeneous Compute Clusters. In: Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, EUC 2014. IEEE; 2014: 146-153.
PUB | DOI | Download (ext.)
 
[29]
2014 | Konferenzbeitrag | PUB-ID: 2681362
Cassano L, Cozzi D, Jungewelter D, et al. An Inter-Processor Communication Interface for Data-Flow Centric Heterogeneous Embedded Multiprocessor Systems. Presented at the DTIS 2014, 9th International conference on Design & Technology of Integrated Systems in Nanoscale Era, Santorini , Greece.
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[28]
2013 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2576115 OA
Korf S, Sievers G, Ax J, et al. Dynamisch rekonfigurierbare Hardware als Basistechnologie für intelligente technische Systeme. In: Proceedings Wissenschaftsforum 2013 Intelligente Technische Systeme. HNI-Verlagsschriftenreihe. 2013: 79-90.
PUB | PDF
 
[27]
2013 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2622226
Sterpone L, Porrmann M, Hagemeyer J. A Novel Fault Tolerant and Runtime Reconfigurable Platform for Satellite Payload Processing. IEEE Transactions on Computers. 2013;62(8):1508-1525.
PUB | DOI | WoS
 
[26]
2013 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2681289
Desogus M, Sterpone L, Porrmann M, Hagemeyer J, Illstad J. Hardening Dynamically Reconfigurable Processing Modules Architectures: A Neutron Test Experience. In: RADECS proceedings. Vol 2. IEEE / Institute of Electrical and Electronics Engineers; 2013: 13-16.
PUB
 
[25]
2013 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2681304
Sterpone L, Sabena D, Ullah A, Porrmann M, Hagemeyer J, Ilstad J. Dynamic neutron testing of Dynamically Reconfigurable Processing Modules architecture. In: Adaptive Hardware and Systems (AHS), 2013 NASA/ESA Conference on. 2013: 184-188.
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[24]
2013 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2576042
Cassano L, Cozzi D, Korf S, Hagemeyer J, Porrmann M, Sterpone L. On-Line Testing of Permanent Radiation Effects in Reconfigurable Systems. In: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013. Piscataway, NJ: IEEE; 2013: 717-720.
PUB | DOI
 
[23]
2012 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2559365
Romoth J, Jungewelter D, Hagemeyer J, Porrmann M, Rückert U. Optimizing inter-FPGA communication by automatic channel adaptation. In: Reconfigurable Computing and FPGAs (ReConFig), 2012 International Conference on. 2012: 1-7.
PUB | DOI
 
[22]
2012 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2517354
Hagemeyer J, Hilgenstein A, Jungewelter D, et al. A Scalable Platform for Run-time Reconfigurable Satellite Payload Processing. In: 2012 NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2012). Piscataway, NJ: IEEE; 2012: 9-16.
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[21]
2011 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493823
Grawinkel M, Schäfers T, Brinkmann A, Hagemeyer J, Porrmann M. Evaluation of Applied Intra-Disk Redundancy Schemes to Improve Single Disk Reliability. In: MASCOTS2011 The 19th Annual Meeting of the IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems. 2011: 297-306.
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[20]
2011 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493819
Sterpone L, Margaglia F, Köster M, Hagemeyer J, Porrmann M. Analysis of SEU Effects in Partially Reconfigurable SoPCs. In: Proceedings of NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2011). 2011: 129-136.
PUB | DOI
 
[19]
2011 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494507
Romoth J, Hagemeyer J, Porrmann M, Rückert U. Fast Design-space Exploration with FPGA Cluster. In: DATE 2011 Workshop on Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing. 2011.
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[18]
2011 | Kurzbeitrag Konferenz / Poster | Veröffentlicht | PUB-ID: 2494497
Köster M, Hagemeyer J, Margaglia F, et al. Design Flow for a Fault-Tolerant Reconfigurable Multi-FPGA Architecture for Space Applications. In: DATE 2011 Workshop on Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing. 2011.
PUB
 
[17]
2011 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286173
Korf S, Cozzi D, Koester M, et al. Automatic HDL-Based Generation of Homogeneous Hard Macros for FPGAs. In: Field-Programmable Custom Computing Machines (FCCM), 2011 IEEE 19th Annual International Symposium on. 2011: 125-132.
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[16]
2010 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493826
Dittmann F, Linke M, Hagemeyer J, et al. Implementation of a Dynamically Reconfigurable Processing Module for SpaceWire Networks. In: Proceedings of the International SpaceWire Conference 2010. 2010: 193-196.
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[15]
2010 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472693 OA
Porrmann M, Hagemeyer J, Pohl C, Romoth J, Strugholtz M. RAPTOR – A Scalable Platform for Rapid Prototyping and FPGA-based Cluster Computing. In: Parallel Computing: From Multicores and GPU's to Petascale, Advances in Parallel Computing. Vol 19. IOS press; 2010: 592-599.
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[14]
2010 | Patent | Veröffentlicht | PUB-ID: 2494087
Christmann W, Strugholtz M, Hagemeyer J, Porrmann M. Mehrprozessor-Computersystem. 2010.
PUB
 
[13]
2010 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2145423
Koester M, Luk W, Hagemeyer J, Porrmann M, Rückert U. Design Optimizations for Tiled Partially Reconfigurable Systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2010;19(6):1048-1061.
PUB | DOI | WoS
 
[12]
2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472673
Koester M, Luk W, Hagemeyer J, Porrmann M. Design Optimizations to Improve Placeability of Partial Reconfiguration Modules. In: Proceedings of the International Conference on Design, Automation and Test in Europe (DATE 2009). ACM Press; 2009.
PUB | DOI | Download (ext.)
 
[11]
2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472678
Porrmann M, Hagemeyer J, Romoth J, Strugholtz M. Rapid Prototyping of Next-Generation Multiprocessor SoCs. In: Proceedings of Semiconductor Conference Dresden, SCD 2009. Dresden, Germany; 2009.
PUB
 
[10]
2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472686
Grassi PR, Santambrogio M, Hagemeyer J, Pohl C, Porrmann M. SiLLis: A Simplified Language for Monitoring and Debugging of Reconfigurable Systems. In: Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '09). Las Vegas, USA; 2009: 174-180.
PUB
 
[9]
2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2144891
Paiz C, Pohl C, Radkowski R, Hagemeyer J, Porrmann M, Rückert U. FPGA-in-the-Loop-Simulations for Dynamically Reconfigurable Applications. In: Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT'09). The University of New South Wales, Sydney, Australia, 9-11, Sydney, Australia; 2009: 372-375.
PUB | DOI
 
[8]
2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2144880
Pohl C, Hagemeyer J, Porrmann M, Rückert U. Using a Reconfigurable Compute Cluster for the Acceleration of Neural Networks. In: Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT '09). Sydney, Australia; 2009: 368-371.
PUB | DOI
 
[7]
2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2144843 OA
Paiz C, Hagemeyer J, Pohl C, et al. FPGA-Based Realization of Self-Optimizing Drive-Controllers. In: the 35th Annual Conference of the IEEE Industrial Electronics Society (IECON 2009). 2009: 2868-2873.
PUB | PDF | DOI | Download (ext.)
 
[6]
2008 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472725
Hagemeyer J, Koester M, Porrmann M. Hardware Virtualization Exploiting Dynamically Reconfigurable Architectures. In: 1. GI/ITG KuVS Fachgespräch Virtualisierung. Heinz Nixdorf Institut, Universität Paderborn; 2008.
PUB
 
[5]
2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472738
Hagemeyer J, Kettelhoit B, Koester M, Porrmann M. Design of Homogeneous Communication Infrastructures for Partially Reconfigurable FPGAs. In: Proc. of the Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA '07). Las Vegas, USA; 2007.
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[4]
2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472729
Schulz B, Paiz C, Hagemeyer J, Mathapati S, Porrmann M, Böcker J. Run-Time Reconfiguration of FPGA-Based Drive Controllers. In: European Conference on Power Electronics and Applications (EPE 2007). Aalborg, Denmark; 2007.
PUB | DOI
 
[3]
2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472743
Hagemeyer J, Kettelhoit B, Koester M, Porrmann M. A Design Methodology for Communication Infrastructures on Partially Reconfigurable FPGAS. In: Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL). Amsterdam, Netherlands; 2007: 331-338.
PUB | DOI
 
[2]
2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472748
Hagemeyer J, Kettelhoit B, Koester M, Porrmann M. INDRA – Integrated Design Flow for Reconfigurable Architectures. In: Proceedings of the Conference on Design, Automation and Test in Europe (DATE '07) – University Booth. 2007.
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[1]
2006 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2473942
Hagemeyer J, Kettelhoit B, Porrmann M. Dedicated Module Access in Dynamically Reconfigurable Systems. In: Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS). 2006.
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