PUB - Publikationen an der Universität Bielefeld

Reconfigurable hardware is gaining a steadily growing interest in the domain of space applications. The ability to reconfigure the information processing infrastructure at runtime together with the high computational power of today's FPGA architectures at relatively low power makes these devices interesting candidates for data processing in space applications. Partial dynamic reconfiguration of FPGAs enables maximum flexibility and can be utilized for performance increase, for improving energy efficiency, and for enhanced fault tolerance. To be able to prove the effectiveness of these novel approaches for satellite payload processing, a highly scalable prototyping environment has been developed, combining dynamically reconfigurable FPGAs with the required interfaces such as SpaceWire, MIL-STD-1553B, and SpaceFibre. Up to 30 SpaceWire interfaces, 5 copper-based SpaceFibre interfaces, and 270 GPIOs can be realized and combined with one to five dynamically reconfigurable Xilinx FPGAs and up to 20 GByte of working memory. The implemented approach for dynamic reconfiguration enables partial reconfiguration at 400 MByte/s. Blind and readback scrubbing is supported and the scrub rate can be adapted individually for different parts of the design.