Hardening Dynamically Reconfigurable Processing Modules Architectures: A Neutron Test Experience
Desogus M, Sterpone L, Porrmann M, Hagemeyer J, Illstad J (2013)
In: RADECS proceedings., 2. IEEE / Institute of Electrical and Electronics Engineers: 13-16.
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Einrichtung
Abstract / Bemerkung
In this paper we describe the hardening of a Dynamically Reconfigurable Processing Module (DRPM) Systems implemented on modern SRAM-based FPGAs. We also report the neutron radiation testing campaigns when the system is implemented on Xilinx Virtex-4 and Virtex-5 SRAM-based FPGAs. Experimental results demonstrate the effectives of the proposed method
Erscheinungsjahr
2013
Titel des Konferenzbandes
RADECS proceedings
Band
2
Seite(n)
13-16
Page URI
https://pub.uni-bielefeld.de/record/2681289
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Desogus M, Sterpone L, Porrmann M, Hagemeyer J, Illstad J. Hardening Dynamically Reconfigurable Processing Modules Architectures: A Neutron Test Experience. In: RADECS proceedings. Vol 2. IEEE / Institute of Electrical and Electronics Engineers; 2013: 13-16.
Desogus, M., Sterpone, L., Porrmann, M., Hagemeyer, J., & Illstad, J. (2013). Hardening Dynamically Reconfigurable Processing Modules Architectures: A Neutron Test Experience. RADECS proceedings, 2, 13-16
Desogus, Marco, Sterpone, Luca, Porrmann, Mario, Hagemeyer, Jens, and Illstad, Jorgen. 2013. “Hardening Dynamically Reconfigurable Processing Modules Architectures: A Neutron Test Experience”. In RADECS proceedings, 2:13-16. IEEE / Institute of Electrical and Electronics Engineers.
Desogus, M., Sterpone, L., Porrmann, M., Hagemeyer, J., and Illstad, J. (2013). “Hardening Dynamically Reconfigurable Processing Modules Architectures: A Neutron Test Experience” in RADECS proceedings, vol. 2, (IEEE / Institute of Electrical and Electronics Engineers), 13-16.
Desogus, M., et al., 2013. Hardening Dynamically Reconfigurable Processing Modules Architectures: A Neutron Test Experience. In RADECS proceedings. no.2 IEEE / Institute of Electrical and Electronics Engineers, pp. 13-16.
M. Desogus, et al., “Hardening Dynamically Reconfigurable Processing Modules Architectures: A Neutron Test Experience”, RADECS proceedings, vol. 2, IEEE / Institute of Electrical and Electronics Engineers, 2013, pp.13-16.
Desogus, M., Sterpone, L., Porrmann, M., Hagemeyer, J., Illstad, J.: Hardening Dynamically Reconfigurable Processing Modules Architectures: A Neutron Test Experience. RADECS proceedings. 2, p. 13-16. IEEE / Institute of Electrical and Electronics Engineers (2013).
Desogus, Marco, Sterpone, Luca, Porrmann, Mario, Hagemeyer, Jens, and Illstad, Jorgen. “Hardening Dynamically Reconfigurable Processing Modules Architectures: A Neutron Test Experience”. RADECS proceedings. IEEE / Institute of Electrical and Electronics Engineers, 2013.Vol. 2. 13-16.
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