PUB - Publikationen an der Universität Bielefeld

In vision processing systems, many applications require multi-camera support. For the connection of the cameras to the processing system, multiple interfaces and a platform capable of handling sustained high data rates are essential. To cope with these requirements, a hardware-based solution using FPGA technology is advisable, especially when targeting space and energy constrained embedded systems. The aim of this work is to develop and implement an FPGA-based scalable and resourceefficient multi-camera GigE Vision IP core for video and image processing. To reduce the number of interfaces needed, the IP core supports the connection of multi-camera interfaces to a single Gigabit Ethernet port using an Ethernet switch. The multicamera GigE Vision IP core is able to extract the raw video data from multiple GigE Vision video streams, reconstruct the video frames from every camera and pass these data for further processing. To test the system, four GigE Vision cameras are used. The IP core is implemented on a Xilinx Virtex-4 FPGA and integrated in a complete video processing platform for a full system realization. In addition to the IP core, bilinear interpolation for image demosaicing with Bayer pattern and an automatic white balance algorithm are implemented for evaluation of the platform. Benchmarking of the hardware implementation has been performed with a total resolution of up to 2048x2048 pixels. Achieved frame rates vary from 25 fps to 345 fps depending on the selected resolution and on the number of used cameras.