A Novel Fault Tolerant and Runtime Reconfigurable Platform for Satellite Payload Processing

Sterpone L, Porrmann M, Hagemeyer J (2013)
IEEE Transactions on Computers 62(8): 1508-1525.

Zeitschriftenaufsatz | Veröffentlicht | Englisch
 
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Abstract / Bemerkung
Reconfigurable hardware is gaining a steadily growing interest in the domain of space applications. The ability to reconfigure the information processing infrastructure at runtime together with the high computational power of today's FPGA architectures at relatively low power makes these devices interesting candidates for data processing in space applications. Partial dynamic reconfiguration of FPGAs enables maximum flexibility and can be utilized for performance optimization, for improving energy efficiency, and for enhanced fault tolerance. To be able to prove the effectiveness of these novel approaches for satellite payload processing, a highly scalable prototyping environment has been developed, combining dynamically reconfigurable FPGAs with the required interfaces such as SpaceWire, MIL-STD-1553B, and SpaceFibre. The developed systems have been enabled to space harsh environments thanks to an analytical analysis of the radiation effects on its most critical reconfigurable components. Aiming at that scope, a new algorithm for the analysis of critical radiation effects, in particular, related to Single Event Upsets (SEUs) and Multiple Event Upsets (MEUs) has been developed to obtain an effective estimation of the radiation impact and enabling the tuning of the component mapping reducing the routing interaction between the reconfigurable placed modules in their different feasible positions. The experimental performance of the system has been evaluated by a proper dynamic reconfiguration scenario, demonstrating a partial reconfiguration at 400 MByte/s, blind and readback scrubbing is supported and the scrub rate can be adapted individually for different parts of the design. The fault tolerance capability has been proven by means of a new analysis algorithm and by fault injection campaigns of SEUs and MCUs into the FPGA configuration memory.
Stichworte
static analysis; fault injection; upsets; multiple event; fault tolerance; single event upsets; FPGA; partial reconfiguration
Erscheinungsjahr
2013
Zeitschriftentitel
IEEE Transactions on Computers
Band
62
Ausgabe
8
Seite(n)
1508-1525
ISSN
0018-9340
Page URI
https://pub.uni-bielefeld.de/record/2622226

Zitieren

Sterpone L, Porrmann M, Hagemeyer J. A Novel Fault Tolerant and Runtime Reconfigurable Platform for Satellite Payload Processing. IEEE Transactions on Computers. 2013;62(8):1508-1525.
Sterpone, L., Porrmann, M., & Hagemeyer, J. (2013). A Novel Fault Tolerant and Runtime Reconfigurable Platform for Satellite Payload Processing. IEEE Transactions on Computers, 62(8), 1508-1525. doi:10.1109/TC.2013.80
Sterpone, L., Porrmann, M., and Hagemeyer, J. (2013). A Novel Fault Tolerant and Runtime Reconfigurable Platform for Satellite Payload Processing. IEEE Transactions on Computers 62, 1508-1525.
Sterpone, L., Porrmann, M., & Hagemeyer, J., 2013. A Novel Fault Tolerant and Runtime Reconfigurable Platform for Satellite Payload Processing. IEEE Transactions on Computers, 62(8), p 1508-1525.
L. Sterpone, M. Porrmann, and J. Hagemeyer, “A Novel Fault Tolerant and Runtime Reconfigurable Platform for Satellite Payload Processing”, IEEE Transactions on Computers, vol. 62, 2013, pp. 1508-1525.
Sterpone, L., Porrmann, M., Hagemeyer, J.: A Novel Fault Tolerant and Runtime Reconfigurable Platform for Satellite Payload Processing. IEEE Transactions on Computers. 62, 1508-1525 (2013).
Sterpone, Luca, Porrmann, Mario, and Hagemeyer, Jens. “A Novel Fault Tolerant and Runtime Reconfigurable Platform for Satellite Payload Processing”. IEEE Transactions on Computers 62.8 (2013): 1508-1525.

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