53 Publikationen

Alle markieren

[53]
2019 | Sammelwerksbeitrag | Veröffentlicht | PUB-ID: 2920469
Oleksiak, A., et al., 2019. M2DC – A Novel Heterogeneous Hyperscale Microserver Platform. In C. Kachris, B. Falsafi, & D. Soudris, eds. Hardware Accelerators in Data Centers. 1st ed. Cham, Switzerland: Springer International Publishing AG, pp. 109-128.
PUB | DOI
 
[52]
2018 | Zeitschriftenaufsatz | E-Veröff. vor dem Druck | PUB-ID: 2920468
Ibraheem, O.W., et al., 2018. FPGA-Based Vision Processing System for Automatic Online Player Tracking in Indoor Sports. Journal of Signal Processing Systems.
PUB | DOI | WoS
 
[51]
2018 | Konferenzbeitrag | PUB-ID: 2921314
Klimeck, D., et al., 2018. Resource-efficient Reconfigurable Computer-on-Module for Embedded Vision Applications. Presented at the 29th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2018), Milan, Italy.
PUB
 
[50]
2018 | Kurzbeitrag Konferenz / Poster | Veröffentlicht | PUB-ID: 2918788 OA
Kaiser, M., et al., 2018. Accelerating Hamming Distance Comparisons for Locality Sensitive Hashing (LSH) using FPGAs. In 12th CeBiTec Symposium - Big Data in Medicine and Biotechnology - Abstract Book. no.12 Bielefeld, pp. 48-49.
PUB | PDF
 
[49]
2017 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2937407
Agosta, G., et al., 2017. The M2DC Approach towards Resource-efficient Computing. In A. Bagnato, et al., eds. OPPORTUNITIES AND CHALLENGES for European Projects. Volume 1: EPS Portugal 2017/2018. Setúbal, Portugal: SCITEPRESS, pp. 150-176.
PUB | DOI
 
[48]
2017 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2912818
Oleksiak, A., et al., 2017. M2DC – Modular Microserver DataCentre with heterogeneous hardware. Microprocessors and Microsystems, 52, p 117-130.
PUB | DOI | WoS
 
[47]
2017 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2912815
Ibraheem, O.W., et al., 2017. Reconfigurable Vision Processing System for Player Tracking in Indoor Sports. In Conference on Design and Architectures for Signal and Image Processing (DASIP 2017). Piscataway, NJ: IEEE, pp. 1-6.
PUB | DOI
 
[46]
2017 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2909430
Irwansyah, A., et al., 2017. FPGA-based Multi-Robot Tracking. Journal of Parallel and Distributed Computing, 107, p 146-161.
PUB | DOI | Download (ext.) | WoS
 
[45]
2017 | Kurzbeitrag Konferenz / Poster | Veröffentlicht | PUB-ID: 2918683 OA
Kaiser, M., et al., 2017. A Reconfigurable Heterogeneous Microserver Architecture for Energy-efficient Computing. In Third International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC'17). Denver, CO.
PUB | PDF | Download (ext.)
 
[44]
2017 | Konferenzbeitrag | PUB-ID: 2909584
Oleksiak, A., et al., 2017. M2DC: Modular Microserver Datacentre with Heterogeneous Hardware. Presented at the Energy-efficient Servers for Cloud and Edge Computing 2017 Workshop (ENeSCE 2017) - co-located with HiPEAC 2017, Stockholm, Sweden.
PUB
 
[43]
2017 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2915029
Tlatlik, J., et al., 2017. Entwurf eines FPGA-basierten Verbindungsknotens als Prototypenumgebung für energieeffiziente und sichere Gebäudeautomationssysteme. In S. - O. Schulze, et al., eds. Tag des Systems Engineering: Paderborn, 8. -10. November 2017. München: Carl Hanser Verlag GmbH Co KG, pp. 55-- 64.
PUB
 
[42]
2017 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2909044
Lachmair, J., et al., 2017. From CPU to FPGA – Acceleration of Self-Organizing Maps for Data Mining. In International Joint Conference on Neural Networks (IJCNN 2017). pp. 4299-4308.
PUB
 
[41]
2016 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2908973
Cozzi, D., et al., 2016. OLT(RE)²: an On-Line on-demand Testing approach for permanent Radiation Effects in REconfigurable systems. IEEE Transactions on Emerging Topics in Computing, PP(99), p 1-1.
PUB | DOI | WoS
 
[40]
2016 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2908974
Oleksiak, A., et al., 2016. Data centres for IoT applications: The M2DC approach (Invited paper). In 2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS). pp. 293-299.
PUB | DOI
 
[39]
2016 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2903257 OA
Kierzynka, M., et al., 2016. Energy Efficiency of Sequence Alignment Tools - Software and Hardware Perspectives. Future Generation Computer Systems, 67, p 455-465.
PUB | PDF | DOI | Download (ext.) | WoS
 
[38]
2016 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2908980
Cecowski, M., et al., 2016. The M2DC Project: Modular Microserver DataCentre. In 2016 Euromicro Conference on Digital System Design (DSD). Institute of Electrical and Electronics Engineers (IEEE).
PUB | DOI
 
[37]
2016 | Kurzbeitrag Konferenz / Poster | PUB-ID: 2909602 OA
Griessl, R., et al., 2016. FiPS and M2DC: Novel Architectures for Reconfigurable Hyperscale Servers. Presented at the Workshop "Reconfigurable Computing — From Embedded Systems to Reconfigurable Hyperscale Servers" co-located with the International Conference on Field-Programmable Logic and Applications (FPL 2016), Lausanne, Switzerland.
PUB | Download (ext.)
 
[36]
2015 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2901108
Irwansyah, A., et al., 2015. FPGA-based circular hough transform with graph clustering for vision-based multi-robot tracking. In ReConFigurable Computing and FPGAs (ReConFig), 2015 International Conference on. IEEE, pp. 1-8.
PUB | DOI
 
[35]
2015 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2901107
Ibraheem, O.W., et al., 2015. A resource-efficient multi-camera GigE vision IP core for embedded vision processing platforms. In ReConFigurable Computing and FPGAs (ReConFig), 2015 International Conference on. IEEE, pp. 1-6.
PUB | DOI
 
[34]
2015 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2902039 OA
Griessl, R., et al., 2015. FPGA-accelerated Heterogeneous Hyperscale Server Architecture for Next-Generation Compute Clusters. Presented at the First International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC‘15), held in conjunction with Supercomputing 2015, Austin Texas, USA.
PUB | PDF
 
[33]
2014 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2681323
Sabena, D., et al., 2014. Reconfigurable High Performance Architectures: How much are they ready for safety-critical applications. In Proceedings of 19th IEEE European Test Symposium (ETS). pp. 175-182.
PUB | DOI | Download (ext.)
 
[32]
2014 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2698999
Sorrenti, D., et al., 2014. Exploiting Dynamic Partial Reconfiguration for On-Line On-Demand Testing of Permanent Faults in Reconfigurable Systems. Presented at the 17th IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Amsterdam, The Netherlands.
PUB | DOI | Download (ext.)
 
[31]
2014 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2699005
Cozzi, D., et al., 2014. AXI-based SpaceFibre IP CORE Implementation. Presented at the 6th International SpaceWire Conference, Athens, Greece.
PUB | DOI | Download (ext.)
 
[30]
2014 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2698930
Griessl, R., et al., 2014. A Scalable Server Architecture for Next-Generation Heterogeneous Compute Clusters. In Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, EUC 2014. IEEE, pp. 146-153.
PUB | DOI | Download (ext.)
 
[29]
2014 | Konferenzbeitrag | PUB-ID: 2681362
Cassano, L., et al., 2014. An Inter-Processor Communication Interface for Data-Flow Centric Heterogeneous Embedded Multiprocessor Systems. Presented at the DTIS 2014, 9th International conference on Design & Technology of Integrated Systems in Nanoscale Era, Santorini , Greece.
PUB | DOI | Download (ext.)
 
[28]
2013 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2576115 OA
Korf, S., et al., 2013. Dynamisch rekonfigurierbare Hardware als Basistechnologie für intelligente technische Systeme. In Proceedings Wissenschaftsforum 2013 Intelligente Technische Systeme. HNI-Verlagsschriftenreihe. pp. 79-90.
PUB | PDF
 
[27]
2013 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2622226
Sterpone, L., Porrmann, M., & Hagemeyer, J., 2013. A Novel Fault Tolerant and Runtime Reconfigurable Platform for Satellite Payload Processing. IEEE Transactions on Computers, 62(8), p 1508-1525.
PUB | DOI | WoS
 
[26]
2013 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2681289
Desogus, M., et al., 2013. Hardening Dynamically Reconfigurable Processing Modules Architectures: A Neutron Test Experience. In RADECS proceedings. no.2 IEEE / Institute of Electrical and Electronics Engineers, pp. 13-16.
PUB
 
[25]
2013 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2681304
Sterpone, L., et al., 2013. Dynamic neutron testing of Dynamically Reconfigurable Processing Modules architecture. In Adaptive Hardware and Systems (AHS), 2013 NASA/ESA Conference on. pp. 184-188.
PUB | DOI | Download (ext.)
 
[24]
2013 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2576042
Cassano, L., et al., 2013. On-Line Testing of Permanent Radiation Effects in Reconfigurable Systems. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013. Piscataway, NJ: IEEE, pp. 717-720.
PUB | DOI
 
[23]
2012 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2559365
Romoth, J., et al., 2012. Optimizing inter-FPGA communication by automatic channel adaptation. In Reconfigurable Computing and FPGAs (ReConFig), 2012 International Conference on. pp. 1-7.
PUB | DOI
 
[22]
2012 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2517354
Hagemeyer, J., et al., 2012. A Scalable Platform for Run-time Reconfigurable Satellite Payload Processing. In 2012 NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2012). Piscataway, NJ: IEEE, pp. 9-16.
PUB | DOI | Download (ext.)
 
[21]
2011 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493823
Grawinkel, M., et al., 2011. Evaluation of Applied Intra-Disk Redundancy Schemes to Improve Single Disk Reliability. In MASCOTS2011 The 19th Annual Meeting of the IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems. pp. 297-306.
PUB | DOI | Download (ext.)
 
[20]
2011 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493819
Sterpone, L., et al., 2011. Analysis of SEU Effects in Partially Reconfigurable SoPCs. In Proceedings of NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2011). pp. 129-136.
PUB | DOI
 
[19]
2011 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494507
Romoth, J., et al., 2011. Fast Design-space Exploration with FPGA Cluster. In DATE 2011 Workshop on Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing.
PUB | Download (ext.)
 
[18]
2011 | Kurzbeitrag Konferenz / Poster | Veröffentlicht | PUB-ID: 2494497
Köster, M., et al., 2011. Design Flow for a Fault-Tolerant Reconfigurable Multi-FPGA Architecture for Space Applications. In DATE 2011 Workshop on Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing.
PUB
 
[17]
2011 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286173
Korf, S., et al., 2011. Automatic HDL-Based Generation of Homogeneous Hard Macros for FPGAs. In Field-Programmable Custom Computing Machines (FCCM), 2011 IEEE 19th Annual International Symposium on. pp. 125-132.
PUB | Download (ext.)
 
[16]
2010 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493826
Dittmann, F., et al., 2010. Implementation of a Dynamically Reconfigurable Processing Module for SpaceWire Networks. In Proceedings of the International SpaceWire Conference 2010. pp. 193-196.
PUB | Download (ext.)
 
[15]
2010 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472693 OA
Porrmann, M., et al., 2010. RAPTOR – A Scalable Platform for Rapid Prototyping and FPGA-based Cluster Computing. In Parallel Computing: From Multicores and GPU's to Petascale, Advances in Parallel Computing. no.19 IOS press, pp. 592-599.
PUB | PDF
 
[14]
2010 | Patent | Veröffentlicht | PUB-ID: 2494087
Christmann, W., et al., 2010. Mehrprozessor-Computersystem.
PUB
 
[13]
2010 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2145423
Koester, M., et al., 2010. Design Optimizations for Tiled Partially Reconfigurable Systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 19(6), p 1048-1061.
PUB | DOI | WoS
 
[12]
2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472673
Koester, M., et al., 2009. Design Optimizations to Improve Placeability of Partial Reconfiguration Modules. In Proceedings of the International Conference on Design, Automation and Test in Europe (DATE 2009). ACM Press.
PUB | DOI | Download (ext.)
 
[11]
2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472678
Porrmann, M., et al., 2009. Rapid Prototyping of Next-Generation Multiprocessor SoCs. In Proceedings of Semiconductor Conference Dresden, SCD 2009. Dresden, Germany.
PUB
 
[10]
2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472686
Grassi, P.R., et al., 2009. SiLLis: A Simplified Language for Monitoring and Debugging of Reconfigurable Systems. In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '09). Las Vegas, USA, pp. 174-180.
PUB
 
[9]
2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2144891
Paiz, C., et al., 2009. FPGA-in-the-Loop-Simulations for Dynamically Reconfigurable Applications. In Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT'09). The University of New South Wales, Sydney, Australia, 9-11, Sydney, Australia, pp. 372-375.
PUB | DOI
 
[8]
2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2144880
Pohl, C., et al., 2009. Using a Reconfigurable Compute Cluster for the Acceleration of Neural Networks. In Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT '09). Sydney, Australia, pp. 368-371.
PUB | DOI
 
[7]
2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2144843 OA
Paiz, C., et al., 2009. FPGA-Based Realization of Self-Optimizing Drive-Controllers. In the 35th Annual Conference of the IEEE Industrial Electronics Society (IECON 2009). pp. 2868-2873.
PUB | PDF | DOI | Download (ext.)
 
[6]
2008 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472725
Hagemeyer, J., Koester, M., & Porrmann, M., 2008. Hardware Virtualization Exploiting Dynamically Reconfigurable Architectures. In 1. GI/ITG KuVS Fachgespräch Virtualisierung. Heinz Nixdorf Institut, Universität Paderborn.
PUB
 
[5]
2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472738
Hagemeyer, J., et al., 2007. Design of Homogeneous Communication Infrastructures for Partially Reconfigurable FPGAs. In Proc. of the Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA '07). Las Vegas, USA.
PUB | Download (ext.)
 
[4]
2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472729
Schulz, B., et al., 2007. Run-Time Reconfiguration of FPGA-Based Drive Controllers. In European Conference on Power Electronics and Applications (EPE 2007). Aalborg, Denmark.
PUB | DOI
 
[3]
2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472743
Hagemeyer, J., et al., 2007. A Design Methodology for Communication Infrastructures on Partially Reconfigurable FPGAS. In Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL). Amsterdam, Netherlands, pp. 331-338.
PUB | DOI
 
[2]
2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472748
Hagemeyer, J., et al., 2007. INDRA – Integrated Design Flow for Reconfigurable Architectures. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE '07) – University Booth.
PUB | Download (ext.)
 
[1]
2006 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2473942
Hagemeyer, J., Kettelhoit, B., & Porrmann, M., 2006. Dedicated Module Access in Dynamically Reconfigurable Systems. In Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS).
PUB | DOI
 

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53 Publikationen

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[53]
2019 | Sammelwerksbeitrag | Veröffentlicht | PUB-ID: 2920469
Oleksiak, A., et al., 2019. M2DC – A Novel Heterogeneous Hyperscale Microserver Platform. In C. Kachris, B. Falsafi, & D. Soudris, eds. Hardware Accelerators in Data Centers. 1st ed. Cham, Switzerland: Springer International Publishing AG, pp. 109-128.
PUB | DOI
 
[52]
2018 | Zeitschriftenaufsatz | E-Veröff. vor dem Druck | PUB-ID: 2920468
Ibraheem, O.W., et al., 2018. FPGA-Based Vision Processing System for Automatic Online Player Tracking in Indoor Sports. Journal of Signal Processing Systems.
PUB | DOI | WoS
 
[51]
2018 | Konferenzbeitrag | PUB-ID: 2921314
Klimeck, D., et al., 2018. Resource-efficient Reconfigurable Computer-on-Module for Embedded Vision Applications. Presented at the 29th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2018), Milan, Italy.
PUB
 
[50]
2018 | Kurzbeitrag Konferenz / Poster | Veröffentlicht | PUB-ID: 2918788 OA
Kaiser, M., et al., 2018. Accelerating Hamming Distance Comparisons for Locality Sensitive Hashing (LSH) using FPGAs. In 12th CeBiTec Symposium - Big Data in Medicine and Biotechnology - Abstract Book. no.12 Bielefeld, pp. 48-49.
PUB | PDF
 
[49]
2017 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2937407
Agosta, G., et al., 2017. The M2DC Approach towards Resource-efficient Computing. In A. Bagnato, et al., eds. OPPORTUNITIES AND CHALLENGES for European Projects. Volume 1: EPS Portugal 2017/2018. Setúbal, Portugal: SCITEPRESS, pp. 150-176.
PUB | DOI
 
[48]
2017 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2912818
Oleksiak, A., et al., 2017. M2DC – Modular Microserver DataCentre with heterogeneous hardware. Microprocessors and Microsystems, 52, p 117-130.
PUB | DOI | WoS
 
[47]
2017 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2912815
Ibraheem, O.W., et al., 2017. Reconfigurable Vision Processing System for Player Tracking in Indoor Sports. In Conference on Design and Architectures for Signal and Image Processing (DASIP 2017). Piscataway, NJ: IEEE, pp. 1-6.
PUB | DOI
 
[46]
2017 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2909430
Irwansyah, A., et al., 2017. FPGA-based Multi-Robot Tracking. Journal of Parallel and Distributed Computing, 107, p 146-161.
PUB | DOI | Download (ext.) | WoS
 
[45]
2017 | Kurzbeitrag Konferenz / Poster | Veröffentlicht | PUB-ID: 2918683 OA
Kaiser, M., et al., 2017. A Reconfigurable Heterogeneous Microserver Architecture for Energy-efficient Computing. In Third International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC'17). Denver, CO.
PUB | PDF | Download (ext.)
 
[44]
2017 | Konferenzbeitrag | PUB-ID: 2909584
Oleksiak, A., et al., 2017. M2DC: Modular Microserver Datacentre with Heterogeneous Hardware. Presented at the Energy-efficient Servers for Cloud and Edge Computing 2017 Workshop (ENeSCE 2017) - co-located with HiPEAC 2017, Stockholm, Sweden.
PUB
 
[43]
2017 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2915029
Tlatlik, J., et al., 2017. Entwurf eines FPGA-basierten Verbindungsknotens als Prototypenumgebung für energieeffiziente und sichere Gebäudeautomationssysteme. In S. - O. Schulze, et al., eds. Tag des Systems Engineering: Paderborn, 8. -10. November 2017. München: Carl Hanser Verlag GmbH Co KG, pp. 55-- 64.
PUB
 
[42]
2017 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2909044
Lachmair, J., et al., 2017. From CPU to FPGA – Acceleration of Self-Organizing Maps for Data Mining. In International Joint Conference on Neural Networks (IJCNN 2017). pp. 4299-4308.
PUB
 
[41]
2016 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2908973
Cozzi, D., et al., 2016. OLT(RE)²: an On-Line on-demand Testing approach for permanent Radiation Effects in REconfigurable systems. IEEE Transactions on Emerging Topics in Computing, PP(99), p 1-1.
PUB | DOI | WoS
 
[40]
2016 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2908974
Oleksiak, A., et al., 2016. Data centres for IoT applications: The M2DC approach (Invited paper). In 2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS). pp. 293-299.
PUB | DOI
 
[39]
2016 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2903257 OA
Kierzynka, M., et al., 2016. Energy Efficiency of Sequence Alignment Tools - Software and Hardware Perspectives. Future Generation Computer Systems, 67, p 455-465.
PUB | PDF | DOI | Download (ext.) | WoS
 
[38]
2016 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2908980
Cecowski, M., et al., 2016. The M2DC Project: Modular Microserver DataCentre. In 2016 Euromicro Conference on Digital System Design (DSD). Institute of Electrical and Electronics Engineers (IEEE).
PUB | DOI
 
[37]
2016 | Kurzbeitrag Konferenz / Poster | PUB-ID: 2909602 OA
Griessl, R., et al., 2016. FiPS and M2DC: Novel Architectures for Reconfigurable Hyperscale Servers. Presented at the Workshop "Reconfigurable Computing — From Embedded Systems to Reconfigurable Hyperscale Servers" co-located with the International Conference on Field-Programmable Logic and Applications (FPL 2016), Lausanne, Switzerland.
PUB | Download (ext.)
 
[36]
2015 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2901108
Irwansyah, A., et al., 2015. FPGA-based circular hough transform with graph clustering for vision-based multi-robot tracking. In ReConFigurable Computing and FPGAs (ReConFig), 2015 International Conference on. IEEE, pp. 1-8.
PUB | DOI
 
[35]
2015 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2901107
Ibraheem, O.W., et al., 2015. A resource-efficient multi-camera GigE vision IP core for embedded vision processing platforms. In ReConFigurable Computing and FPGAs (ReConFig), 2015 International Conference on. IEEE, pp. 1-6.
PUB | DOI
 
[34]
2015 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2902039 OA
Griessl, R., et al., 2015. FPGA-accelerated Heterogeneous Hyperscale Server Architecture for Next-Generation Compute Clusters. Presented at the First International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC‘15), held in conjunction with Supercomputing 2015, Austin Texas, USA.
PUB | PDF
 
[33]
2014 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2681323
Sabena, D., et al., 2014. Reconfigurable High Performance Architectures: How much are they ready for safety-critical applications. In Proceedings of 19th IEEE European Test Symposium (ETS). pp. 175-182.
PUB | DOI | Download (ext.)
 
[32]
2014 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2698999
Sorrenti, D., et al., 2014. Exploiting Dynamic Partial Reconfiguration for On-Line On-Demand Testing of Permanent Faults in Reconfigurable Systems. Presented at the 17th IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Amsterdam, The Netherlands.
PUB | DOI | Download (ext.)
 
[31]
2014 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2699005
Cozzi, D., et al., 2014. AXI-based SpaceFibre IP CORE Implementation. Presented at the 6th International SpaceWire Conference, Athens, Greece.
PUB | DOI | Download (ext.)
 
[30]
2014 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2698930
Griessl, R., et al., 2014. A Scalable Server Architecture for Next-Generation Heterogeneous Compute Clusters. In Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, EUC 2014. IEEE, pp. 146-153.
PUB | DOI | Download (ext.)
 
[29]
2014 | Konferenzbeitrag | PUB-ID: 2681362
Cassano, L., et al., 2014. An Inter-Processor Communication Interface for Data-Flow Centric Heterogeneous Embedded Multiprocessor Systems. Presented at the DTIS 2014, 9th International conference on Design & Technology of Integrated Systems in Nanoscale Era, Santorini , Greece.
PUB | DOI | Download (ext.)
 
[28]
2013 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2576115 OA
Korf, S., et al., 2013. Dynamisch rekonfigurierbare Hardware als Basistechnologie für intelligente technische Systeme. In Proceedings Wissenschaftsforum 2013 Intelligente Technische Systeme. HNI-Verlagsschriftenreihe. pp. 79-90.
PUB | PDF
 
[27]
2013 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2622226
Sterpone, L., Porrmann, M., & Hagemeyer, J., 2013. A Novel Fault Tolerant and Runtime Reconfigurable Platform for Satellite Payload Processing. IEEE Transactions on Computers, 62(8), p 1508-1525.
PUB | DOI | WoS
 
[26]
2013 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2681289
Desogus, M., et al., 2013. Hardening Dynamically Reconfigurable Processing Modules Architectures: A Neutron Test Experience. In RADECS proceedings. no.2 IEEE / Institute of Electrical and Electronics Engineers, pp. 13-16.
PUB
 
[25]
2013 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2681304
Sterpone, L., et al., 2013. Dynamic neutron testing of Dynamically Reconfigurable Processing Modules architecture. In Adaptive Hardware and Systems (AHS), 2013 NASA/ESA Conference on. pp. 184-188.
PUB | DOI | Download (ext.)
 
[24]
2013 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2576042
Cassano, L., et al., 2013. On-Line Testing of Permanent Radiation Effects in Reconfigurable Systems. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013. Piscataway, NJ: IEEE, pp. 717-720.
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[23]
2012 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2559365
Romoth, J., et al., 2012. Optimizing inter-FPGA communication by automatic channel adaptation. In Reconfigurable Computing and FPGAs (ReConFig), 2012 International Conference on. pp. 1-7.
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[22]
2012 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2517354
Hagemeyer, J., et al., 2012. A Scalable Platform for Run-time Reconfigurable Satellite Payload Processing. In 2012 NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2012). Piscataway, NJ: IEEE, pp. 9-16.
PUB | DOI | Download (ext.)
 
[21]
2011 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493823
Grawinkel, M., et al., 2011. Evaluation of Applied Intra-Disk Redundancy Schemes to Improve Single Disk Reliability. In MASCOTS2011 The 19th Annual Meeting of the IEEE International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems. pp. 297-306.
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[20]
2011 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493819
Sterpone, L., et al., 2011. Analysis of SEU Effects in Partially Reconfigurable SoPCs. In Proceedings of NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2011). pp. 129-136.
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[19]
2011 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2494507
Romoth, J., et al., 2011. Fast Design-space Exploration with FPGA Cluster. In DATE 2011 Workshop on Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing.
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[18]
2011 | Kurzbeitrag Konferenz / Poster | Veröffentlicht | PUB-ID: 2494497
Köster, M., et al., 2011. Design Flow for a Fault-Tolerant Reconfigurable Multi-FPGA Architecture for Space Applications. In DATE 2011 Workshop on Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing.
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[17]
2011 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286173
Korf, S., et al., 2011. Automatic HDL-Based Generation of Homogeneous Hard Macros for FPGAs. In Field-Programmable Custom Computing Machines (FCCM), 2011 IEEE 19th Annual International Symposium on. pp. 125-132.
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[16]
2010 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2493826
Dittmann, F., et al., 2010. Implementation of a Dynamically Reconfigurable Processing Module for SpaceWire Networks. In Proceedings of the International SpaceWire Conference 2010. pp. 193-196.
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[15]
2010 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472693 OA
Porrmann, M., et al., 2010. RAPTOR – A Scalable Platform for Rapid Prototyping and FPGA-based Cluster Computing. In Parallel Computing: From Multicores and GPU's to Petascale, Advances in Parallel Computing. no.19 IOS press, pp. 592-599.
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[14]
2010 | Patent | Veröffentlicht | PUB-ID: 2494087
Christmann, W., et al., 2010. Mehrprozessor-Computersystem.
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[13]
2010 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2145423
Koester, M., et al., 2010. Design Optimizations for Tiled Partially Reconfigurable Systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 19(6), p 1048-1061.
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[12]
2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472673
Koester, M., et al., 2009. Design Optimizations to Improve Placeability of Partial Reconfiguration Modules. In Proceedings of the International Conference on Design, Automation and Test in Europe (DATE 2009). ACM Press.
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[11]
2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472678
Porrmann, M., et al., 2009. Rapid Prototyping of Next-Generation Multiprocessor SoCs. In Proceedings of Semiconductor Conference Dresden, SCD 2009. Dresden, Germany.
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[10]
2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472686
Grassi, P.R., et al., 2009. SiLLis: A Simplified Language for Monitoring and Debugging of Reconfigurable Systems. In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '09). Las Vegas, USA, pp. 174-180.
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[9]
2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2144891
Paiz, C., et al., 2009. FPGA-in-the-Loop-Simulations for Dynamically Reconfigurable Applications. In Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT'09). The University of New South Wales, Sydney, Australia, 9-11, Sydney, Australia, pp. 372-375.
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[8]
2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2144880
Pohl, C., et al., 2009. Using a Reconfigurable Compute Cluster for the Acceleration of Neural Networks. In Proceedings of the 2009 International Conference on Field-Programmable Technology (FPT '09). Sydney, Australia, pp. 368-371.
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[7]
2009 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2144843 OA
Paiz, C., et al., 2009. FPGA-Based Realization of Self-Optimizing Drive-Controllers. In the 35th Annual Conference of the IEEE Industrial Electronics Society (IECON 2009). pp. 2868-2873.
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[6]
2008 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472725
Hagemeyer, J., Koester, M., & Porrmann, M., 2008. Hardware Virtualization Exploiting Dynamically Reconfigurable Architectures. In 1. GI/ITG KuVS Fachgespräch Virtualisierung. Heinz Nixdorf Institut, Universität Paderborn.
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[5]
2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472738
Hagemeyer, J., et al., 2007. Design of Homogeneous Communication Infrastructures for Partially Reconfigurable FPGAs. In Proc. of the Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA '07). Las Vegas, USA.
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[4]
2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472729
Schulz, B., et al., 2007. Run-Time Reconfiguration of FPGA-Based Drive Controllers. In European Conference on Power Electronics and Applications (EPE 2007). Aalborg, Denmark.
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[3]
2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472743
Hagemeyer, J., et al., 2007. A Design Methodology for Communication Infrastructures on Partially Reconfigurable FPGAS. In Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL). Amsterdam, Netherlands, pp. 331-338.
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[2]
2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2472748
Hagemeyer, J., et al., 2007. INDRA – Integrated Design Flow for Reconfigurable Architectures. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE '07) – University Booth.
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[1]
2006 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2473942
Hagemeyer, J., Kettelhoit, B., & Porrmann, M., 2006. Dedicated Module Access in Dynamically Reconfigurable Systems. In Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS).
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