PUB - Publikationen an der Universität Bielefeld

Clusters of FPGAs are a promising environment for prototyping and evaluation of new MPSoC architectures with a large number of parallel cores. The high complexity of both the MPSoC and the FPGA cluster pose many challenges for the designer [1]. Tools like Synopsys Certify can be used to automatically partition designs on systems with a fixed communication infrastructure, still they do not address the problem that minor changes in the design might require a whole rerun of the mapping procedure. For each FPGA the architecture mapping consists of synthesis, place & route, bitstream generation, and finally the FPGA configuration. While the configuration is done within milliseconds, synthesis, place & route, and bitstream generation easily take several hours to complete. Thus, the evaluation of different architectural variants becomes a very time-consuming task.