Design Flow for a Fault-Tolerant Reconfigurable Multi-FPGA Architecture for Space Applications
Köster M, Hagemeyer J, Margaglia F, Porrmann M, Dittmann F, Ditze M, Sterpone L, Harris J, Ilstad J (2011)
In: DATE 2011 Workshop on Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing.
Kurzbeitrag Konferenz / Poster
| Veröffentlicht | Englisch
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Autor*in
Köster, Markus;
Hagemeyer, JensUniBi;
Margaglia, Fabio;
Porrmann, MarioUniBi 
;
Dittmann, Florian;
Ditze, Michael;
Sterpone, Luca;
Harris, Julian;
Ilstad, Jorgen
;
Dittmann, Florian;
Ditze, Michael;
Sterpone, Luca;
Harris, Julian;
Ilstad, JorgenEinrichtung
Erscheinungsjahr
2011
Titel des Konferenzbandes
DATE 2011 Workshop on Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing
Konferenzort
Grenoble, France
Konferenzdatum
March 18 - 21
Page URI
https://pub.uni-bielefeld.de/record/2494497
Zitieren
Köster M, Hagemeyer J, Margaglia F, et al. Design Flow for a Fault-Tolerant Reconfigurable Multi-FPGA Architecture for Space Applications. In: DATE 2011 Workshop on Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing. 2011.
Köster, M., Hagemeyer, J., Margaglia, F., Porrmann, M., Dittmann, F., Ditze, M., Sterpone, L., et al. (2011). Design Flow for a Fault-Tolerant Reconfigurable Multi-FPGA Architecture for Space Applications. DATE 2011 Workshop on Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing
Köster, Markus, Hagemeyer, Jens, Margaglia, Fabio, Porrmann, Mario, Dittmann, Florian, Ditze, Michael, Sterpone, Luca, Harris, Julian, and Ilstad, Jorgen. 2011. “Design Flow for a Fault-Tolerant Reconfigurable Multi-FPGA Architecture for Space Applications”. In DATE 2011 Workshop on Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing.
Köster, M., Hagemeyer, J., Margaglia, F., Porrmann, M., Dittmann, F., Ditze, M., Sterpone, L., Harris, J., and Ilstad, J. (2011). “Design Flow for a Fault-Tolerant Reconfigurable Multi-FPGA Architecture for Space Applications” in DATE 2011 Workshop on Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing.
Köster, M., et al., 2011. Design Flow for a Fault-Tolerant Reconfigurable Multi-FPGA Architecture for Space Applications. In DATE 2011 Workshop on Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing.
M. Köster, et al., “Design Flow for a Fault-Tolerant Reconfigurable Multi-FPGA Architecture for Space Applications”, DATE 2011 Workshop on Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing, 2011.
Köster, M., Hagemeyer, J., Margaglia, F., Porrmann, M., Dittmann, F., Ditze, M., Sterpone, L., Harris, J., Ilstad, J.: Design Flow for a Fault-Tolerant Reconfigurable Multi-FPGA Architecture for Space Applications. DATE 2011 Workshop on Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing. (2011).
Köster, Markus, Hagemeyer, Jens, Margaglia, Fabio, Porrmann, Mario, Dittmann, Florian, Ditze, Michael, Sterpone, Luca, Harris, Julian, and Ilstad, Jorgen. “Design Flow for a Fault-Tolerant Reconfigurable Multi-FPGA Architecture for Space Applications”. DATE 2011 Workshop on Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing. 2011.
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