PUB - Publikationen an der Universität Bielefeld

The ability of partial reconfiguration of today's FPGAs allows the exchange of dynamic system components at runtime, which enables the realization of self-reconfigurable systems. To ease the design of a partially reconfigurable system this paper presents an integrated design flow for reconfigurable architectures. The design flow includes tools for system partitioning, floorplanning, and automatic generation of configuration data for the static and the dynamic system components. Furthermore, the design flow comprises the implementation of a homogeneous on-chip communication infrastructure, which is used to interconnect the dynamic system components placed at run-time. For the design of such an on-chip communication infrastructure a layer model is introduced, which divides the communication into five different layers of abstraction. As an example a communication infrastructure is realized on a Xilinx Virtex-2 FPGA based on the Wishbone protocol. A tristate-based and a slice-based implementation are presented and analyzed with respect to efficiency.