Gregor Sievers
PEVZ-ID
14 Publikationen
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2016 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2900363
Performance Estimation of Streaming Applications for Hierarchical MPSoCsPUB | PDF | DOI
Flasskamp, Martin, Performance Estimation of Streaming Applications for Hierarchical MPSoCs. Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO) (). New York, NY, 2016 -
2016 | Bielefelder E-Dissertation | PUB-ID: 2904773
Entwurfsraumexploration eng gekoppelter paralleler RechnerarchitekturenPUB | PDF
Sievers, Gregor, Entwurfsraumexploration eng gekoppelter paralleler Rechnerarchitekturen. (). Bielefeld, 2016 -
2015 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2783142
System-Level Analysis of Network Interfaces for Hierarchical MPSoCsPUB | PDF | DOI
Ax, Johannes, System-Level Analysis of Network Interfaces for Hierarchical MPSoCs. Proceedings of the 8th International Workshop on Network on Chip Architectures (NoCArc) (). New York, NY, USA, 2015 -
2015 | Report | PUB-ID: 2783874
An Abstract Model for Performance Estimation of the Embedded Multiprocessor CoreVA-MPSoC Technical Report (v1.0)PUB | PDF
Ax, Johannes, An Abstract Model for Performance Estimation of the Embedded Multiprocessor CoreVA-MPSoC Technical Report (v1.0). (). , 2015 -
2015 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2760622Comparison of Shared and Private L1 Data Memories for an Embedded MPSoC in 28nm FD-SOIPUB | DOI
Sievers, Gregor, Comparison of Shared and Private L1 Data Memories for an Embedded MPSoC in 28nm FD-SOI. International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC) (). , 2015 -
2015 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2732427Evaluation of Interconnect Fabrics for an Embedded MPSoC in 28 nm FD-SOIPUB | DOI | Download (ext.)
Sievers, Gregor, Evaluation of Interconnect Fabrics for an Embedded MPSoC in 28 nm FD-SOI. 2015 IEEE International Symposium on Circuits & Systems (ISCAS) (). , 2015 -
2014 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2698929CoreVA: A Configurable Resource-efficient VLIW Processor ArchitecturePUB | DOI
Hübener, Boris, CoreVA: A Configurable Resource-efficient VLIW Processor Architecture. Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing (). , 2014 -
2014 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2753235A Communication Model and Partitioning Algorithm for Streaming Applications for an Embedded MPSoCPUB | DOI | Download (ext.)
Kelly, Wayne, A Communication Model and Partitioning Algorithm for Streaming Applications for an Embedded MPSoC. International Symposium on System-on-Chip (SoC) (). Tampere, Finland, 2014 -
2013 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2576115
Dynamisch rekonfigurierbare Hardware als Basistechnologie für intelligente technische SystemePUB | PDF
Korf, Sebastian, Dynamisch rekonfigurierbare Hardware als Basistechnologie für intelligente technische Systeme. Proceedings Wissenschaftsforum 2013 Intelligente Technische Systeme 310 (). Paderborn, 2013 -
2013 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2637667Design-Space Exploration of the Configurable 32 bit VLIW Processor CoreVA for Signal Processing ApplicationsPUB | DOI
Sievers, Gregor, Design-Space Exploration of the Configurable 32 bit VLIW Processor CoreVA for Signal Processing Applications. 2013 NORCHIP (). , 2013 -
2013 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2634649Pareto-optimal Signal Processing on Low-Power MicroprocessorsPUB | DOI | Download (ext.)
Christ, Peter, Pareto-optimal Signal Processing on Low-Power Microprocessors. Proceedings of the 12th IEEE International Conference on SENSORS (). , 2013 -
2011 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2476993
Resource Efficiency of Scalable Processor Architectures for SDR-based Applications (Invited)PUB | Dateien verfügbar
Jungeblut, Thorsten, Resource Efficiency of Scalable Processor Architectures for SDR-based Applications (Invited). Proc. of the Radar, Communication and Measurement Conference (RADCOM) (). , 2011 -
2010 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2018549Design Space Exploration for Memory Subsystems of VLIW ArchitecturesPUB | DOI
Jungeblut, Thorsten, Design Space Exploration for Memory Subsystems of VLIW Architectures. 5th IEEE International Conference on Networking, Architecture, and Storage (). , 2010 -
2010 | Konferenzbeitrag | PUB-ID: 2286628
A modular design flow for very large design space explorationsPUB | Dateien verfügbar
Jungeblut, Thorsten, A modular design flow for very large design space explorations. (). , 2010