PUB - Publikationen an der Universität Bielefeld

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• [14]
  

  2016 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2900363

  M. Flasskamp, et al., “Performance Estimation of Streaming Applications for Hierarchical MPSoCs”, Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO), New York, NY: ACM Press, 2016, pp.1.

  PUB | PDF | DOI
   
• [13]
  

  2016 | Bielefelder E-Dissertation | PUB-ID: 2904773

  G. Sievers, Entwurfsraumexploration eng gekoppelter paralleler Rechnerarchitekturen, Bielefeld: Universität Bielefeld, 2016.

  PUB | PDF
   
• [12]
  

  2015 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2783142

  J. Ax, et al., “System-Level Analysis of Network Interfaces for Hierarchical MPSoCs”, Proceedings of the 8th International Workshop on Network on Chip Architectures (NoCArc), New York, NY, USA: ACM, 2015, pp.3-8.

  PUB | PDF | DOI
   
• [11]
  

  2015 | Report | PUB-ID: 2783874

  J. Ax, et al., An Abstract Model for Performance Estimation of the Embedded Multiprocessor CoreVA-MPSoC Technical Report (v1.0), 2015.

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• [10]
  

  2015 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2760622

  G. Sievers, et al., “Comparison of Shared and Private L1 Data Memories for an Embedded MPSoC in 28nm FD-SOI”, International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), IEEE, 2015, pp.175-181.

  PUB | DOI
   
• [9]
  

  2015 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2732427

  G. Sievers, et al., “Evaluation of Interconnect Fabrics for an Embedded MPSoC in 28 nm FD-SOI”, 2015 IEEE International Symposium on Circuits & Systems (ISCAS), IEEE, 2015, pp.1925-1928.

  PUB | DOI | Download (ext.)
   
• [8]
  

  2014 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2698929

  B. Hübener, et al., “CoreVA: A Configurable Resource-efficient VLIW Processor Architecture”, Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, IEEE, 2014, pp.9-16.

  PUB | DOI
   
• [7]
  

  2014 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2753235

  W. Kelly, et al., “A Communication Model and Partitioning Algorithm for Streaming Applications for an Embedded MPSoC”, International Symposium on System-on-Chip (SoC), Tampere, Finland: IEEE, 2014.

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• [6]
  

  2013 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2576115

  S. Korf, et al., “Dynamisch rekonfigurierbare Hardware als Basistechnologie für intelligente technische Systeme”, Proceedings Wissenschaftsforum 2013 Intelligente Technische Systeme, J. Gausemeier, et al., eds., HNI-Verlagsschriftenreihe, vol. 310, Paderborn: Heinz-Nixdorf-Inst., Univ. Paderborn, 2013, pp.79-90.

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• [5]
  

  2013 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2637667

  G. Sievers, et al., “Design-Space Exploration of the Configurable 32 bit VLIW Processor CoreVA for Signal Processing Applications”, 2013 NORCHIP, 2013.

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• [4]
  

  2013 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2634649

  P. Christ, et al., “Pareto-optimal Signal Processing on Low-Power Microprocessors”, Proceedings of the 12th IEEE International Conference on SENSORS, IEEE, 2013, pp.1843-1846.

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• [3]
  

  2011 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2476993

  T. Jungeblut, et al., “Resource Efficiency of Scalable Processor Architectures for SDR-based Applications (Invited)”, Proc. of the Radar, Communication and Measurement Conference (RADCOM), 2011.

  PUB | Dateien verfügbar
   
• [2]
  

  2010 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2018549

  T. Jungeblut, et al., “Design Space Exploration for Memory Subsystems of VLIW Architectures”, 5th IEEE International Conference on Networking, Architecture, and Storage, 2010, pp.377-385.

  PUB | DOI
   
• [1]
  

  2010 | Konferenzbeitrag | PUB-ID: 2286628

  T. Jungeblut, et al., “A modular design flow for very large design space explorations”, CDNLive! EMEA 2010, 2010.

  PUB | Dateien verfügbar