14 Publikationen

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[14]
2016 | Bielefelder E-Dissertation | PUB-ID: 2904773 OA
Sievers, G., 2016. Entwurfsraumexploration eng gekoppelter paralleler Rechnerarchitekturen, Bielefeld: Universität Bielefeld.
PUB | PDF
 
[13]
2016 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2900363 OA
Flasskamp, M., et al., 2016. Performance Estimation of Streaming Applications for Hierarchical MPSoCs. In Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO). New York, NY: ACM Press, pp. 1.
PUB | PDF | DOI
 
[12]
2015 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2732427
Sievers, G., et al., 2015. Evaluation of Interconnect Fabrics for an Embedded MPSoC in 28 nm FD-SOI. In 2015 IEEE International Symposium on Circuits & Systems (ISCAS). IEEE, pp. 1925-1928.
PUB | DOI | Download (ext.)
 
[11]
2015 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2760622
Sievers, G., et al., 2015. Comparison of Shared and Private L1 Data Memories for an Embedded MPSoC in 28nm FD-SOI. In International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC). IEEE, pp. 175-181.
PUB | DOI
 
[10]
2015 | Report | PUB-ID: 2783874 OA
Ax, J., et al., 2015. An Abstract Model for Performance Estimation of the Embedded Multiprocessor CoreVA-MPSoC Technical Report (v1.0),
PUB | PDF
 
[9]
2015 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2783142 OA
Ax, J., et al., 2015. System-Level Analysis of Network Interfaces for Hierarchical MPSoCs. In Proceedings of the 8th International Workshop on Network on Chip Architectures (NoCArc). New York, NY, USA: ACM, pp. 3-8.
PUB | PDF | DOI
 
[8]
2014 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2698929
Hübener, B., et al., 2014. CoreVA: A Configurable Resource-efficient VLIW Processor Architecture. In Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing. IEEE, pp. 9-16.
PUB | DOI
 
[7]
2014 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2753235
Kelly, W., et al., 2014. A Communication Model and Partitioning Algorithm for Streaming Applications for an Embedded MPSoC. In International Symposium on System-on-Chip (SoC). Tampere, Finland: IEEE.
PUB | DOI | Download (ext.)
 
[6]
2013 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2576115 OA
Korf, S., et al., 2013. Dynamisch rekonfigurierbare Hardware als Basistechnologie für intelligente technische Systeme. In J. Gausemeier, et al., eds. Proceedings Wissenschaftsforum 2013 Intelligente Technische Systeme. HNI-Verlagsschriftenreihe. no.310 Paderborn: Heinz-Nixdorf-Inst., Univ. Paderborn, pp. 79-90.
PUB | PDF
 
[5]
2013 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2637667
Sievers, G., et al., 2013. Design-Space Exploration of the Configurable 32 bit VLIW Processor CoreVA for Signal Processing Applications. In 2013 NORCHIP.
PUB | DOI
 
[4]
2013 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2634649
Christ, P., et al., 2013. Pareto-optimal Signal Processing on Low-Power Microprocessors. In Proceedings of the 12th IEEE International Conference on SENSORS. IEEE, pp. 1843-1846.
PUB | DOI | Download (ext.)
 
[3]
2011 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2476993 OA
Jungeblut, T., et al., 2011. Resource Efficiency of Scalable Processor Architectures for SDR-based Applications (Invited). In Proc. of the Radar, Communication and Measurement Conference (RADCOM).
PUB | Dateien verfügbar
 
[2]
2010 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2018549
Jungeblut, T., et al., 2010. Design Space Exploration for Memory Subsystems of VLIW Architectures. In 5th IEEE International Conference on Networking, Architecture, and Storage. pp. 377-385.
PUB | DOI
 
[1]
2010 | Konferenzbeitrag | PUB-ID: 2286628 OA
Jungeblut, T., et al., 2010. A modular design flow for very large design space explorations.
PUB | Dateien verfügbar
 

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14 Publikationen

Alle markieren

[14]
2016 | Bielefelder E-Dissertation | PUB-ID: 2904773 OA
Sievers, G., 2016. Entwurfsraumexploration eng gekoppelter paralleler Rechnerarchitekturen, Bielefeld: Universität Bielefeld.
PUB | PDF
 
[13]
2016 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2900363 OA
Flasskamp, M., et al., 2016. Performance Estimation of Streaming Applications for Hierarchical MPSoCs. In Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO). New York, NY: ACM Press, pp. 1.
PUB | PDF | DOI
 
[12]
2015 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2732427
Sievers, G., et al., 2015. Evaluation of Interconnect Fabrics for an Embedded MPSoC in 28 nm FD-SOI. In 2015 IEEE International Symposium on Circuits & Systems (ISCAS). IEEE, pp. 1925-1928.
PUB | DOI | Download (ext.)
 
[11]
2015 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2760622
Sievers, G., et al., 2015. Comparison of Shared and Private L1 Data Memories for an Embedded MPSoC in 28nm FD-SOI. In International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC). IEEE, pp. 175-181.
PUB | DOI
 
[10]
2015 | Report | PUB-ID: 2783874 OA
Ax, J., et al., 2015. An Abstract Model for Performance Estimation of the Embedded Multiprocessor CoreVA-MPSoC Technical Report (v1.0),
PUB | PDF
 
[9]
2015 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2783142 OA
Ax, J., et al., 2015. System-Level Analysis of Network Interfaces for Hierarchical MPSoCs. In Proceedings of the 8th International Workshop on Network on Chip Architectures (NoCArc). New York, NY, USA: ACM, pp. 3-8.
PUB | PDF | DOI
 
[8]
2014 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2698929
Hübener, B., et al., 2014. CoreVA: A Configurable Resource-efficient VLIW Processor Architecture. In Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing. IEEE, pp. 9-16.
PUB | DOI
 
[7]
2014 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2753235
Kelly, W., et al., 2014. A Communication Model and Partitioning Algorithm for Streaming Applications for an Embedded MPSoC. In International Symposium on System-on-Chip (SoC). Tampere, Finland: IEEE.
PUB | DOI | Download (ext.)
 
[6]
2013 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2576115 OA
Korf, S., et al., 2013. Dynamisch rekonfigurierbare Hardware als Basistechnologie für intelligente technische Systeme. In J. Gausemeier, et al., eds. Proceedings Wissenschaftsforum 2013 Intelligente Technische Systeme. HNI-Verlagsschriftenreihe. no.310 Paderborn: Heinz-Nixdorf-Inst., Univ. Paderborn, pp. 79-90.
PUB | PDF
 
[5]
2013 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2637667
Sievers, G., et al., 2013. Design-Space Exploration of the Configurable 32 bit VLIW Processor CoreVA for Signal Processing Applications. In 2013 NORCHIP.
PUB | DOI
 
[4]
2013 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2634649
Christ, P., et al., 2013. Pareto-optimal Signal Processing on Low-Power Microprocessors. In Proceedings of the 12th IEEE International Conference on SENSORS. IEEE, pp. 1843-1846.
PUB | DOI | Download (ext.)
 
[3]
2011 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2476993 OA
Jungeblut, T., et al., 2011. Resource Efficiency of Scalable Processor Architectures for SDR-based Applications (Invited). In Proc. of the Radar, Communication and Measurement Conference (RADCOM).
PUB | Dateien verfügbar
 
[2]
2010 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2018549
Jungeblut, T., et al., 2010. Design Space Exploration for Memory Subsystems of VLIW Architectures. In 5th IEEE International Conference on Networking, Architecture, and Storage. pp. 377-385.
PUB | DOI
 
[1]
2010 | Konferenzbeitrag | PUB-ID: 2286628 OA
Jungeblut, T., et al., 2010. A modular design flow for very large design space explorations.
PUB | Dateien verfügbar
 

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Zitationsstil: harvard1

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