A Multiprocessor Cache for Massively Parallel SoC Architectures

Niemann J-C, Liß C, Porrmann M, Rückert U (2007)
In: ARCS'07: Architecture of Computing Systems. Lukowicz P (Ed); Lecture Notes in Computer Science, 4415. Zurich, Switzerland: Springer Berlin Heidelberg: 83-97.

Konferenzbeitrag | Veröffentlicht | Englisch
 
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Autor*in
Niemann, Jörg-Christian; Liß, Christian; Porrmann, MarioUniBi ; Rückert, UlrichUniBi
Herausgeber*in
Lukowicz, Paul
Abstract / Bemerkung
In this paper, we present an advanced multiprocessor cache architecture for chip multiprocessors (CMPs). It is designed for the scalable GigaNetIC CMP, which is based on massively parallel on-chip computing clusters. Our write-through multiprocessor cache is configurable in respect to the most relevant design options. It is supposed to be used in universal co-processors as well as in network processing units. For an early verification of the software and an early exploration of various hardware configurations, we have developed a SystemC-based simulation model for the complete chip multiprocessor. For detailed hardware-software co-verification, we use our FPGA-based rapid prototyping system RAPTOR2000 to emulate our architecture with near-ASIC performance. Finally, we demonstrate the performance gains for different application scenarios enabled by the usage of our multiprocessor cache.
Erscheinungsjahr
2007
Titel des Konferenzbandes
ARCS'07: Architecture of Computing Systems
Band
4415
Seite(n)
83-97
ISBN
9783540712671
Page URI
https://pub.uni-bielefeld.de/record/2289049

Zitieren

Niemann J-C, Liß C, Porrmann M, Rückert U. A Multiprocessor Cache for Massively Parallel SoC Architectures. In: Lukowicz P, ed. ARCS'07: Architecture of Computing Systems. Lecture Notes in Computer Science. Vol 4415. Zurich, Switzerland: Springer Berlin Heidelberg; 2007: 83-97.
Niemann, J. - C., Liß, C., Porrmann, M., & Rückert, U. (2007). A Multiprocessor Cache for Massively Parallel SoC Architectures. In P. Lukowicz (Ed.), Lecture Notes in Computer Science: Vol. 4415. ARCS'07: Architecture of Computing Systems (pp. 83-97). Zurich, Switzerland: Springer Berlin Heidelberg. doi:10.1007/978-3-540-71270-1_7
Niemann, J. - C., Liß, C., Porrmann, M., and Rückert, U. (2007). “A Multiprocessor Cache for Massively Parallel SoC Architectures” in ARCS'07: Architecture of Computing Systems, Lukowicz, P. ed. Lecture Notes in Computer Science, vol. 4415, (Zurich, Switzerland: Springer Berlin Heidelberg), 83-97.
Niemann, J.-C., et al., 2007. A Multiprocessor Cache for Massively Parallel SoC Architectures. In P. Lukowicz, ed. ARCS'07: Architecture of Computing Systems. Lecture Notes in Computer Science. no.4415 Zurich, Switzerland: Springer Berlin Heidelberg, pp. 83-97.
J.-C. Niemann, et al., “A Multiprocessor Cache for Massively Parallel SoC Architectures”, ARCS'07: Architecture of Computing Systems, P. Lukowicz, ed., Lecture Notes in Computer Science, vol. 4415, Zurich, Switzerland: Springer Berlin Heidelberg, 2007, pp.83-97.
Niemann, J.-C., Liß, C., Porrmann, M., Rückert, U.: A Multiprocessor Cache for Massively Parallel SoC Architectures. In: Lukowicz, P. (ed.) ARCS'07: Architecture of Computing Systems. Lecture Notes in Computer Science. 4415, p. 83-97. Springer Berlin Heidelberg, Zurich, Switzerland (2007).
Niemann, Jörg-Christian, Liß, Christian, Porrmann, Mario, and Rückert, Ulrich. “A Multiprocessor Cache for Massively Parallel SoC Architectures”. ARCS'07: Architecture of Computing Systems. Ed. Paul Lukowicz. Zurich, Switzerland: Springer Berlin Heidelberg, 2007.Vol. 4415. Lecture Notes in Computer Science. 83-97.

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