GigaNetIC – A Scalable Embedded On-Chip Multiprocessor Architecture for Network Applications

Niemann J-C, Puttmann C, Porrmann M, Rückert U (2006)
In: ARCS'06 Architecture of Computing Systems. Grass W (Ed); Lecture notes in computer science, 3894. Berlin, Heidelberg: Springer Berlin Heidelberg: 268-282.

Konferenzbeitrag | Veröffentlicht | Englisch
 
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Autor*in
Niemann, Jörg-Christian; Puttmann, Christoph; Porrmann, MarioUniBi ; Rückert, UlrichUniBi
Herausgeber*in
Grass, Werner
Abstract / Bemerkung
In this paper, we present the prototypical implementation of the scalable GigaNetIC chip multiprocessor architecture. We use an FPGA-based rapid prototyping system to verify the functionality of our architecture in a network application scenario before we are going to fabricate the ASIC in a modern CMOS standard cell technology. The rapid prototyping environment gives us the opportunity to test our multiprocessor architecture with Ethernet-based data streams in a real network scenario. Our system concept is based on a massively parallel processor structure. Due to its regularity, our architecture can be easily scaled to accommodate a wide range of packet processing applications with disparate performance and throughput requirements at high reliability. Furthermore, the composition from predefined building blocks guarantees fast design cycles and simplifies system verification. We present standard cell synthesis results as well as a performance analysis for a firewall application with various couplings of hardware accelerators.
Erscheinungsjahr
2006
Titel des Konferenzbandes
ARCS'06 Architecture of Computing Systems
Band
3894
Seite(n)
268-282
ISBN
9783540327653
ISSN
0302-9743
Page URI
https://pub.uni-bielefeld.de/record/2288961

Zitieren

Niemann J-C, Puttmann C, Porrmann M, Rückert U. GigaNetIC – A Scalable Embedded On-Chip Multiprocessor Architecture for Network Applications. In: Grass W, ed. ARCS'06 Architecture of Computing Systems. Lecture notes in computer science. Vol 3894. Berlin, Heidelberg: Springer Berlin Heidelberg; 2006: 268-282.
Niemann, J. - C., Puttmann, C., Porrmann, M., & Rückert, U. (2006). GigaNetIC – A Scalable Embedded On-Chip Multiprocessor Architecture for Network Applications. In W. Grass (Ed.), Lecture notes in computer science: Vol. 3894. ARCS'06 Architecture of Computing Systems (pp. 268-282). Berlin, Heidelberg: Springer Berlin Heidelberg. doi:10.1007/11682127_19
Niemann, J. - C., Puttmann, C., Porrmann, M., and Rückert, U. (2006). “GigaNetIC – A Scalable Embedded On-Chip Multiprocessor Architecture for Network Applications” in ARCS'06 Architecture of Computing Systems, Grass, W. ed. Lecture notes in computer science, vol. 3894, (Berlin, Heidelberg: Springer Berlin Heidelberg), 268-282.
Niemann, J.-C., et al., 2006. GigaNetIC – A Scalable Embedded On-Chip Multiprocessor Architecture for Network Applications. In W. Grass, ed. ARCS'06 Architecture of Computing Systems. Lecture notes in computer science. no.3894 Berlin, Heidelberg: Springer Berlin Heidelberg, pp. 268-282.
J.-C. Niemann, et al., “GigaNetIC – A Scalable Embedded On-Chip Multiprocessor Architecture for Network Applications”, ARCS'06 Architecture of Computing Systems, W. Grass, ed., Lecture notes in computer science, vol. 3894, Berlin, Heidelberg: Springer Berlin Heidelberg, 2006, pp.268-282.
Niemann, J.-C., Puttmann, C., Porrmann, M., Rückert, U.: GigaNetIC – A Scalable Embedded On-Chip Multiprocessor Architecture for Network Applications. In: Grass, W. (ed.) ARCS'06 Architecture of Computing Systems. Lecture notes in computer science. 3894, p. 268-282. Springer Berlin Heidelberg, Berlin, Heidelberg (2006).
Niemann, Jörg-Christian, Puttmann, Christoph, Porrmann, Mario, and Rückert, Ulrich. “GigaNetIC – A Scalable Embedded On-Chip Multiprocessor Architecture for Network Applications”. ARCS'06 Architecture of Computing Systems. Ed. Werner Grass. Berlin, Heidelberg: Springer Berlin Heidelberg, 2006.Vol. 3894. Lecture notes in computer science. 268-282.

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