Implementation of a RISC Processor Core for SoC Designs – FPGA Prototype vs. ASIC Implementation

Langen D, Niemann J-C, Porrmann M, Kalte H, Rückert U (2002)
In: Proceedings of the IEEE-Workshop: Heterogeneous reconfigurable Systems on Chip (SoC). Hamburg, Germany.

Konferenzbeitrag | Veröffentlicht| Englisch
 
Download
OA
Autor/in
Langen, Dominik; Niemann, Jörg-Christian; Porrmann, MarioUniBi ; Kalte, Heiko; Rückert, UlrichUniBi
Abstract / Bemerkung
In this paper, an implementation of a RISC processor core for SoC designs is presented. We analyze the differences between a prototypical FPGA implementation and standard cell realizations in an 0.6μm and an 0.13μm technology, respectively. The core was developed by using the hardware description language VHDL, which offers the opportunity of adding special, optimized hardware blocks for various operations. The effects on area and power consumption as well as computational power are analyzed. A detailed overview of the implementation of additional hardware multipliers and their effects on the above mentioned topics concludes this paper.
Erscheinungsjahr
2002
Titel des Konferenzbandes
Proceedings of the IEEE-Workshop: Heterogeneous reconfigurable Systems on Chip (SoC)
Page URI
https://pub.uni-bielefeld.de/record/2288565

Zitieren

Langen D, Niemann J-C, Porrmann M, Kalte H, Rückert U. Implementation of a RISC Processor Core for SoC Designs – FPGA Prototype vs. ASIC Implementation. In: Proceedings of the IEEE-Workshop: Heterogeneous reconfigurable Systems on Chip (SoC). Hamburg, Germany; 2002.
Langen, D., Niemann, J. - C., Porrmann, M., Kalte, H., & Rückert, U. (2002). Implementation of a RISC Processor Core for SoC Designs – FPGA Prototype vs. ASIC Implementation. Proceedings of the IEEE-Workshop: Heterogeneous reconfigurable Systems on Chip (SoC) Hamburg, Germany.
Langen, D., Niemann, J. - C., Porrmann, M., Kalte, H., and Rückert, U. (2002). “Implementation of a RISC Processor Core for SoC Designs – FPGA Prototype vs. ASIC Implementation” in Proceedings of the IEEE-Workshop: Heterogeneous reconfigurable Systems on Chip (SoC) (Hamburg, Germany).
Langen, D., et al., 2002. Implementation of a RISC Processor Core for SoC Designs – FPGA Prototype vs. ASIC Implementation. In Proceedings of the IEEE-Workshop: Heterogeneous reconfigurable Systems on Chip (SoC). Hamburg, Germany.
D. Langen, et al., “Implementation of a RISC Processor Core for SoC Designs – FPGA Prototype vs. ASIC Implementation”, Proceedings of the IEEE-Workshop: Heterogeneous reconfigurable Systems on Chip (SoC), Hamburg, Germany: 2002.
Langen, D., Niemann, J.-C., Porrmann, M., Kalte, H., Rückert, U.: Implementation of a RISC Processor Core for SoC Designs – FPGA Prototype vs. ASIC Implementation. Proceedings of the IEEE-Workshop: Heterogeneous reconfigurable Systems on Chip (SoC). Hamburg, Germany (2002).
Langen, Dominik, Niemann, Jörg-Christian, Porrmann, Mario, Kalte, Heiko, and Rückert, Ulrich. “Implementation of a RISC Processor Core for SoC Designs – FPGA Prototype vs. ASIC Implementation”. Proceedings of the IEEE-Workshop: Heterogeneous reconfigurable Systems on Chip (SoC). Hamburg, Germany, 2002.
Alle Dateien verfügbar unter der/den folgenden Lizenz(en):
Copyright Statement:
This Item is protected by copyright and/or related rights. [...]
Volltext(e)
Access Level
OA Open Access
Zuletzt Hochgeladen
2019-09-06T08:57:35Z
MD5 Prüfsumme
59e286a28fece7e8074df09b4dd7b717

Export

Markieren/ Markierung löschen
Markierte Publikationen

Open Data PUB

Suchen in

Google Scholar