GigaNoC - A Hierarchical Network-on-Chip for Scalable Chip-Multiprocessors

Puttmann C, Niemann J-C, Porrmann M, Rückert U (2007)
In: 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007). Piscataway, NJ: IEEE: 495-502.

Konferenzbeitrag | Veröffentlicht | Englisch
 
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Autor*in
Puttmann, Christoph; Niemann, Jörg-Christian; Porrmann, MarioUniBi ; Rückert, UlrichUniBi
Abstract / Bemerkung
Due to the technological progress in the semiconductor industry, more and more components can be integrated on a single die forming a complex System-on-Chip. For enabling an efficient interaction between the various building blocks of today’s SoCs, efficient communication structures become more and more essential. In this paper, we present the GigaNoC, a hierarchical Network-on-Chip that is especially suitable for scalable Chip-Multiprocessor architectures. The GigaNoC approach features a packet-switched wormhole routing on-chip network that provides the backbone of our multiprocessor architecture. In order to meet bandwidth requirements of different application domains, our Network-on-Chip is easily scalable and parameterizable in various aspects. This work highlights the communication protocol and shows a performance evaluation for different congestion scenarios. Furthermore, we present an FPGA-based prototypical realization and introduce a debugging and verification environment. Finally, implementation results for a standard cell technology are discussed.
Stichworte
multiprocessor architecture; FPGA; GigaNoC; scalable chip-multiprocessors; standard cell technology; performance evaluation; field programmable gate arrays; network-on-chip; performance evaluation; field programmable gate arrays; packet-switched wormhole routing on-chip network; network routing; network-on-chip
Erscheinungsjahr
2007
Titel des Konferenzbandes
10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)
Seite(n)
495 -502
Konferenz
10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)
Konferenzort
Lübeck
Konferenzdatum
2007-08-29 – 2007-08-31
ISBN
978-0-7695-2978-3
Page URI
https://pub.uni-bielefeld.de/record/2286362

Zitieren

Puttmann C, Niemann J-C, Porrmann M, Rückert U. GigaNoC - A Hierarchical Network-on-Chip for Scalable Chip-Multiprocessors. In: 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007). Piscataway, NJ: IEEE; 2007: 495-502.
Puttmann, C., Niemann, J. - C., Porrmann, M., & Rückert, U. (2007). GigaNoC - A Hierarchical Network-on-Chip for Scalable Chip-Multiprocessors. 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007), 495-502. Piscataway, NJ: IEEE. doi:10.1109/dsd.2007.4341514
Puttmann, C., Niemann, J. - C., Porrmann, M., and Rückert, U. (2007). “GigaNoC - A Hierarchical Network-on-Chip for Scalable Chip-Multiprocessors” in 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007) (Piscataway, NJ: IEEE), 495-502.
Puttmann, C., et al., 2007. GigaNoC - A Hierarchical Network-on-Chip for Scalable Chip-Multiprocessors. In 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007). Piscataway, NJ: IEEE, pp. 495-502.
C. Puttmann, et al., “GigaNoC - A Hierarchical Network-on-Chip for Scalable Chip-Multiprocessors”, 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007), Piscataway, NJ: IEEE, 2007, pp.495-502.
Puttmann, C., Niemann, J.-C., Porrmann, M., Rückert, U.: GigaNoC - A Hierarchical Network-on-Chip for Scalable Chip-Multiprocessors. 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007). p. 495-502. IEEE, Piscataway, NJ (2007).
Puttmann, Christoph, Niemann, Jörg-Christian, Porrmann, Mario, and Rückert, Ulrich. “GigaNoC - A Hierarchical Network-on-Chip for Scalable Chip-Multiprocessors”. 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007). Piscataway, NJ: IEEE, 2007. 495-502.
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