A scalable parallel SoC architecture for network processors
Niemann J-G, Porrmann M, Rückert U (2005)
In: VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on. IEEE: 311-313.
Konferenzbeitrag
| Veröffentlicht | Englisch
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Abstract / Bemerkung
Information processing and networking of technical devices
find their way into our daily life. In order to process the
continuously growing quantity of data, powerful communication
nodes for network processing are needed. We present an
architecture for network processors that is based on a uniform,
massively parallel structure. Thus, our approach takes
advantage of reusing predefined IP building blocks. This
leads to a short time to market, a high reliability and a scalable
architecture. Our architecture is scalable to different
areas of application by varying the number of integrated
processors. Additionally, specific hardware accelerators can
be embedded, which are optimized for the target application,
in order to be especially resource-efficient in respect to power
consumption, computational power and required area.
Stichworte
parallel structure;
network processors;
integrated processors;
computational power;
parallel architectures;
scalable parallel SoC architecture;
integrated circuit reliability;
circuit optimisation;
system-on-chip;
embedded hardware accelerators
Erscheinungsjahr
2005
Titel des Konferenzbandes
VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on
Seite(n)
311-313
ISBN
076952365X
Page URI
https://pub.uni-bielefeld.de/record/2286309
Zitieren
Niemann J-G, Porrmann M, Rückert U. A scalable parallel SoC architecture for network processors. In: VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on. IEEE; 2005: 311-313.
Niemann, J. - G., Porrmann, M., & Rückert, U. (2005). A scalable parallel SoC architecture for network processors. VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on, 311-313. IEEE. https://doi.org/10.1109/ISVLSI.2005.13
Niemann, J.-G., Porrmann, Mario, and Rückert, Ulrich. 2005. “A scalable parallel SoC architecture for network processors”. In VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on, 311-313. IEEE.
Niemann, J. - G., Porrmann, M., and Rückert, U. (2005). “A scalable parallel SoC architecture for network processors” in VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on (IEEE), 311-313.
Niemann, J.-G., Porrmann, M., & Rückert, U., 2005. A scalable parallel SoC architecture for network processors. In VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on. IEEE, pp. 311-313.
J.-G. Niemann, M. Porrmann, and U. Rückert, “A scalable parallel SoC architecture for network processors”, VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on, IEEE, 2005, pp.311-313.
Niemann, J.-G., Porrmann, M., Rückert, U.: A scalable parallel SoC architecture for network processors. VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on. p. 311-313. IEEE (2005).
Niemann, J.-G., Porrmann, Mario, and Rückert, Ulrich. “A scalable parallel SoC architecture for network processors”. VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on. IEEE, 2005. 311-313.
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