On-chip interconnects for next generation system-on-chips

Brinkmann A, Niemann J-C, Hehemann I, Langen D, Porrmann M, Rückert U (2002)
In: ASIC/SOC Conference, 2002. 15th Annual IEEE International. 211-215.

Konferenzbeitrag | Veröffentlicht| Englisch
 
Download
Es wurde kein Volltext hochgeladen. Nur Publikationsnachweis!
Autor/in
Brinkmann, A.; Niemann, J.-C.; Hehemann, I.; Langen, D.; Porrmann, MarioUniBi ; Rückert, UlrichUniBi
Abstract / Bemerkung
Today's deep submicron fabrication technologies enable design enginefrs to put an impressive number of eomponfnts like micropmeessors, memories, and interfaces on a single microchip. With the emergence of 100 nm processes, billions oftransistors can be integrated on one die and form a parallel system, consisting out of thousands of components. To handle this impressive number of components it is important to provide a communication infrastructure which is able to scale with the capabilities of upcoming fabrication technologies and which provides the foundation for efficient on-chip communication protocols. This paper addresses the architectural requirements which are coupled with the transfer of well known techniques from parallel computers unto the design of Secs and proposes an on-chip architecture which is based on active switch bores. We will show that this architecture is able lo fill the existing design gap between an efficient use of the design space and the design complexity with reasonable resource requirements.
Stichworte
on-chip communication protocols; scalable communication infrastructures; scheduling protocols; system-on-chip architectures; integrated circuit design; integrated circuit modelling; integrated circuit interconnections; logic design; circuit simulation; logic simulation; 100 nm; system-on-chip; multiprocessor interconnection networks; SOC on-chip interconnects; parallel architectures; processor scheduling; routing protocols; active switch boxes; packet switching; design space/complexity/resource requirements; single microchip microprocessors/memories/interfaces; parallel processing; parallel systems; parallel computers; packet routing communication
Erscheinungsjahr
2002
Titel des Konferenzbandes
ASIC/SOC Conference, 2002. 15th Annual IEEE International
Seite(n)
211-215
Page URI
https://pub.uni-bielefeld.de/record/2285966

Zitieren

Brinkmann A, Niemann J-C, Hehemann I, Langen D, Porrmann M, Rückert U. On-chip interconnects for next generation system-on-chips. In: ASIC/SOC Conference, 2002. 15th Annual IEEE International. 2002: 211-215.
Brinkmann, A., Niemann, J. - C., Hehemann, I., Langen, D., Porrmann, M., & Rückert, U. (2002). On-chip interconnects for next generation system-on-chips. ASIC/SOC Conference, 2002. 15th Annual IEEE International, 211-215. doi:10.1109/ASIC.2002.1158058
Brinkmann, A., Niemann, J. - C., Hehemann, I., Langen, D., Porrmann, M., and Rückert, U. (2002). “On-chip interconnects for next generation system-on-chips” in ASIC/SOC Conference, 2002. 15th Annual IEEE International 211-215.
Brinkmann, A., et al., 2002. On-chip interconnects for next generation system-on-chips. In ASIC/SOC Conference, 2002. 15th Annual IEEE International. pp. 211-215.
A. Brinkmann, et al., “On-chip interconnects for next generation system-on-chips”, ASIC/SOC Conference, 2002. 15th Annual IEEE International, 2002, pp.211-215.
Brinkmann, A., Niemann, J.-C., Hehemann, I., Langen, D., Porrmann, M., Rückert, U.: On-chip interconnects for next generation system-on-chips. ASIC/SOC Conference, 2002. 15th Annual IEEE International. p. 211-215. (2002).
Brinkmann, A., Niemann, J.-C., Hehemann, I., Langen, D., Porrmann, Mario, and Rückert, Ulrich. “On-chip interconnects for next generation system-on-chips”. ASIC/SOC Conference, 2002. 15th Annual IEEE International. 2002. 211-215.

Export

Markieren/ Markierung löschen
Markierte Publikationen

Open Data PUB

Suchen in

Google Scholar