Implementation of artificial neural networks on a reconfigurable hardware accelerator

Porrmann M, Witkowski U, Kalte H, Rückert U (2002)
In: Parallel, Distributed and Network-based Processing, 2002. Proceedings. 10th Euromicro Workshop on. IEEE Comput. Soc: 243-250.

Konferenzbeitrag | Veröffentlicht | Englisch
 
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Autor*in
Porrmann, MarioUniBi ; Witkowski, U.; Kalte, H.; Rückert, UlrichUniBi
Abstract / Bemerkung
The hardware implementation of three different artificial neural networks is presented. The basis for the implementation is the reconfigurable hardware accelerator RAPTOR2000, which is based on FPGAs. The investigated neural network architectures are neural associative memories, self-organizing feature maps and basis function networks. Some of the key implementational issues are considered. Especially resource-efficiency and performance of the presented realizations are discussed.
Stichworte
reconfigurable architectures; self-organising feature maps; performance evaluation; neural net architecture; radial basis function networks; RAPTOR2000; FPGA-based system; content-addressable storage; neural chips; system-on-chip; field programmable gate arrays; self-organizing feature maps; reconfigurable hardware accelerator; neural architectures; resource efficiency; performance; neural associative memories; hardware implementation; implementation issues; artificial neural networks; basis function networks
Erscheinungsjahr
2002
Titel des Konferenzbandes
Parallel, Distributed and Network-based Processing, 2002. Proceedings. 10th Euromicro Workshop on
Seite(n)
243 -250
ISBN
0769514448
Page URI
https://pub.uni-bielefeld.de/record/2285896

Zitieren

Porrmann M, Witkowski U, Kalte H, Rückert U. Implementation of artificial neural networks on a reconfigurable hardware accelerator. In: Parallel, Distributed and Network-based Processing, 2002. Proceedings. 10th Euromicro Workshop on. IEEE Comput. Soc; 2002: 243-250.
Porrmann, M., Witkowski, U., Kalte, H., & Rückert, U. (2002). Implementation of artificial neural networks on a reconfigurable hardware accelerator. Parallel, Distributed and Network-based Processing, 2002. Proceedings. 10th Euromicro Workshop on, 243-250. IEEE Comput. Soc. doi:10.1109/EMPDP.2002.994279
Porrmann, M., Witkowski, U., Kalte, H., and Rückert, U. (2002). “Implementation of artificial neural networks on a reconfigurable hardware accelerator” in Parallel, Distributed and Network-based Processing, 2002. Proceedings. 10th Euromicro Workshop on (IEEE Comput. Soc), 243-250.
Porrmann, M., et al., 2002. Implementation of artificial neural networks on a reconfigurable hardware accelerator. In Parallel, Distributed and Network-based Processing, 2002. Proceedings. 10th Euromicro Workshop on. IEEE Comput. Soc, pp. 243-250.
M. Porrmann, et al., “Implementation of artificial neural networks on a reconfigurable hardware accelerator”, Parallel, Distributed and Network-based Processing, 2002. Proceedings. 10th Euromicro Workshop on, IEEE Comput. Soc, 2002, pp.243-250.
Porrmann, M., Witkowski, U., Kalte, H., Rückert, U.: Implementation of artificial neural networks on a reconfigurable hardware accelerator. Parallel, Distributed and Network-based Processing, 2002. Proceedings. 10th Euromicro Workshop on. p. 243-250. IEEE Comput. Soc (2002).
Porrmann, Mario, Witkowski, U., Kalte, H., and Rückert, Ulrich. “Implementation of artificial neural networks on a reconfigurable hardware accelerator”. Parallel, Distributed and Network-based Processing, 2002. Proceedings. 10th Euromicro Workshop on. IEEE Comput. Soc, 2002. 243-250.

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