Implementation of Self-Organizing Feature Maps in Reconfigurable Hardware

Porrmann M, Witkowski U, Rückert U (2006)
In: FPGA Implementations of Neural Networks. Omondi A, Rajapakse J (Eds); Boston, MA: Springer: 247-269.

Sammelwerksbeitrag | Veröffentlicht | Englisch
 
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Autor*in
Herausgeber*in
Omondi, Amos; Rajapakse, Jagath
Abstract / Bemerkung
In this chapter we discuss an implementation of self-organizing feature maps in reconfigurable hardware. Based on the universal rapid prototyping system RAPTOR2000 a hardware accelerator for self-organizing feature maps has been developed. Using state of the art Xilinx FPGAs, RAPTOR2000 is capable of emulating hardware implementations with a complexity of more than 15 million system gates. RAPTOR2000 is linked to its host – a standard personal computer or workstation – via the PCI bus. For the simulation of self-organizing feature maps a module has been designed for the RAPTOR2000 system, that embodies an FPGA of the Xilinx Virtex (-E) series and optionally up to 128 MBytes of SDRAM. A speed-up of up to 190 is achieved with five FPGA modules on the RAPTOR2000 system compared to a software implementation on a state of the art personal computer for typical applications of self-organizing feature maps.
Erscheinungsjahr
2006
Buchtitel
FPGA Implementations of Neural Networks
Seite(n)
247-269
ISBN
978-0-387-28485-9
Page URI
https://pub.uni-bielefeld.de/record/2285718

Zitieren

Porrmann M, Witkowski U, Rückert U. Implementation of Self-Organizing Feature Maps in Reconfigurable Hardware. In: Omondi A, Rajapakse J, eds. FPGA Implementations of Neural Networks. Boston, MA: Springer; 2006: 247-269.
Porrmann, M., Witkowski, U., & Rückert, U. (2006). Implementation of Self-Organizing Feature Maps in Reconfigurable Hardware. In A. Omondi & J. Rajapakse (Eds.), FPGA Implementations of Neural Networks (pp. 247-269). Boston, MA: Springer. doi:10.1007/0-387-28487-7_9
Porrmann, M., Witkowski, U., and Rückert, U. (2006). “Implementation of Self-Organizing Feature Maps in Reconfigurable Hardware” in FPGA Implementations of Neural Networks, Omondi, A., and Rajapakse, J. eds. (Boston, MA: Springer), 247-269.
Porrmann, M., Witkowski, U., & Rückert, U., 2006. Implementation of Self-Organizing Feature Maps in Reconfigurable Hardware. In A. Omondi & J. Rajapakse, eds. FPGA Implementations of Neural Networks. Boston, MA: Springer, pp. 247-269.
M. Porrmann, U. Witkowski, and U. Rückert, “Implementation of Self-Organizing Feature Maps in Reconfigurable Hardware”, FPGA Implementations of Neural Networks, A. Omondi and J. Rajapakse, eds., Boston, MA: Springer, 2006, pp.247-269.
Porrmann, M., Witkowski, U., Rückert, U.: Implementation of Self-Organizing Feature Maps in Reconfigurable Hardware. In: Omondi, A. and Rajapakse, J. (eds.) FPGA Implementations of Neural Networks. p. 247-269. Springer, Boston, MA (2006).
Porrmann, Mario, Witkowski, Ulf, and Rückert, Ulrich. “Implementation of Self-Organizing Feature Maps in Reconfigurable Hardware”. FPGA Implementations of Neural Networks. Ed. Amos Omondi and Jagath Rajapakse. Boston, MA: Springer, 2006. 247-269.

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