A Massively Parallel Architecture for Self-Organizing Feature Maps
Porrmann M, Witkowski U, Rückert U (2003)
IEEE Transactions on Neural Networks, Special Issue on Hardware Implementations 14(5): 1110-1121.
Zeitschriftenaufsatz
| Veröffentlicht | Englisch
Download
Es wurden keine Dateien hochgeladen. Nur Publikationsnachweis!
Autor*in
Abstract / Bemerkung
A hardware accelerator for self-organizing feature maps is presented. We have developed a massively parallel architecture that, on the one hand, allows a resource-efficient implementation of small or medium-sized maps for embedded applications, requiring only small areas of silicon. On the other hand, large maps can be simulated with systems that consist of several integrated circuits that work in parallel. Apart from the learning and recall of self-organizing feature maps, the hardware accelerates data pre- and postprocessing. For the verification of our architectural concepts in a real-world environment, we have implemented an ASIC that is integrated into our heterogeneous multiprocessor system for neural applications. The performance of our system is analyzed for various simulation parameters. Additionally, the performance that can be achieved with future microelectronic technologies is estimated.
Erscheinungsjahr
2003
Zeitschriftentitel
IEEE Transactions on Neural Networks, Special Issue on Hardware Implementations
Band
14
Ausgabe
5
Seite(n)
1110-1121
ISSN
1045-9227
Page URI
https://pub.uni-bielefeld.de/record/2145324
Zitieren
Porrmann M, Witkowski U, Rückert U. A Massively Parallel Architecture for Self-Organizing Feature Maps. IEEE Transactions on Neural Networks, Special Issue on Hardware Implementations. 2003;14(5):1110-1121.
Porrmann, M., Witkowski, U., & Rückert, U. (2003). A Massively Parallel Architecture for Self-Organizing Feature Maps. IEEE Transactions on Neural Networks, Special Issue on Hardware Implementations, 14(5), 1110-1121. https://doi.org/10.1109/TNN.2003.816368
Porrmann, Mario, Witkowski, Ulf, and Rückert, Ulrich. 2003. “A Massively Parallel Architecture for Self-Organizing Feature Maps”. IEEE Transactions on Neural Networks, Special Issue on Hardware Implementations 14 (5): 1110-1121.
Porrmann, M., Witkowski, U., and Rückert, U. (2003). A Massively Parallel Architecture for Self-Organizing Feature Maps. IEEE Transactions on Neural Networks, Special Issue on Hardware Implementations 14, 1110-1121.
Porrmann, M., Witkowski, U., & Rückert, U., 2003. A Massively Parallel Architecture for Self-Organizing Feature Maps. IEEE Transactions on Neural Networks, Special Issue on Hardware Implementations, 14(5), p 1110-1121.
M. Porrmann, U. Witkowski, and U. Rückert, “A Massively Parallel Architecture for Self-Organizing Feature Maps”, IEEE Transactions on Neural Networks, Special Issue on Hardware Implementations, vol. 14, 2003, pp. 1110-1121.
Porrmann, M., Witkowski, U., Rückert, U.: A Massively Parallel Architecture for Self-Organizing Feature Maps. IEEE Transactions on Neural Networks, Special Issue on Hardware Implementations. 14, 1110-1121 (2003).
Porrmann, Mario, Witkowski, Ulf, and Rückert, Ulrich. “A Massively Parallel Architecture for Self-Organizing Feature Maps”. IEEE Transactions on Neural Networks, Special Issue on Hardware Implementations 14.5 (2003): 1110-1121.
Daten bereitgestellt von European Bioinformatics Institute (EBI)
4 Zitationen in Europe PMC
Daten bereitgestellt von Europe PubMed Central.
A Novel Hardware Systolic Architecture of a Self-Organizing Map Neural Network.
Ben Khalifa K, Blaiech AG, Bedoui MH., Comput Intell Neurosci 2019(), 2019
PMID: 31065255
Ben Khalifa K, Blaiech AG, Bedoui MH., Comput Intell Neurosci 2019(), 2019
PMID: 31065255
Improved Learning Performance of Hardware Self-Organizing Map Using a Novel Neighborhood Function.
Hikawa H, Maeda Y., IEEE Trans Neural Netw Learn Syst 26(11), 2015
PMID: 26484943
Hikawa H, Maeda Y., IEEE Trans Neural Netw Learn Syst 26(11), 2015
PMID: 26484943
FPGA implementation of self organizing map with digital phase locked loops.
Hikawa H., Neural Netw 18(5-6), 2005
PMID: 16095877
Hikawa H., Neural Netw 18(5-6), 2005
PMID: 16095877
Color clustering and learning for image segmentation based on neural networks.
Dong G, Xie M., IEEE Trans Neural Netw 16(4), 2005
PMID: 16121733
Dong G, Xie M., IEEE Trans Neural Netw 16(4), 2005
PMID: 16121733
26 References
Daten bereitgestellt von Europe PubMed Central.
AUTHOR UNKNOWN, 0
knowledge extraction from self-organizing neural networks
ultsch, Information and Classification (), 1993
ultsch, Information and Classification (), 1993
som accelerator system
rüping, Neurocomputing 21(), 1998
rüping, Neurocomputing 21(), 1998
som hardware-accelerator
rüping, WSOM 97 Workshop on Self-Organizing Maps (), 1997
rüping, WSOM 97 Workshop on Self-Organizing Maps (), 1997
AUTHOR UNKNOWN, 0
a hybrid knowledge processing system
porrmann, Proc Conf “ Neural Networks Applications” NEURAP98 (), 1998
porrmann, Proc Conf “ Neural Networks Applications” NEURAP98 (), 1998
porrmann, Leistungsbewertung Eingebetteter Neurocomputersysteme (), 2002
AUTHOR UNKNOWN, 0
Modified self-organizing feature map algorithms for efficient digital hardware implementation.
Ienne P, Thiran P, Vassilas N., IEEE Trans Neural Netw 8(2), 1997
PMID: 18255635
Ienne P, Thiran P, Vassilas N., IEEE Trans Neural Netw 8(2), 1997
PMID: 18255635
AUTHOR UNKNOWN, 0
AUTHOR UNKNOWN, 0
AUTHOR UNKNOWN, 0
kohonen, Self-Organizing Maps (), 1995
AUTHOR UNKNOWN, 0
positioning system for the minirobot khepera based on self-organizing feature maps
witkowski, Proc 2002 FIRA Robot World Congress (), 2002
witkowski, Proc 2002 FIRA Robot World Congress (), 2002
seiffert, Self-Organizing Neural Networks – Recent Advances and Applications (), 2001
digital connectionist hardware: current problems and future challenges
ienne, Biological and Artificial Computation From Neuroscience to Technology (), 1997
ienne, Biological and Artificial Computation From Neuroscience to Technology (), 1997
AUTHOR UNKNOWN, 0
hardware implementation of self-organizing maps and associative memory on the minirobot khepera
witkowski, Autonomous Minirobots for Research and Edutainment (AMiRE 2001) (), 2001
witkowski, Autonomous Minirobots for Research and Edutainment (AMiRE 2001) (), 2001
AUTHOR UNKNOWN, 0
a digital vlsi architecture for real world applications
hammerstrom, An Introduction to Neural and Electronic Networks (), 1995
hammerstrom, An Introduction to Neural and Electronic Networks (), 1995
a fast kohonen net implementation for spert-ii
asanovic, Biological and Artificial Computation From Neuroscience to Technology International Work Conference on Artificial and Natural Neural Networks IWANN 97 (), 1997
asanovic, Biological and Artificial Computation From Neuroscience to Technology International Work Conference on Artificial and Natural Neural Networks IWANN 97 (), 1997
AUTHOR UNKNOWN, 0
AUTHOR UNKNOWN, 0
dynamically reconfigurable hardware – a new perspective for neural network implementations
porrmann, Proc 12th Int l Conf Field Programmable Logic and Applications (), 2002
porrmann, Proc 12th Int l Conf Field Programmable Logic and Applications (), 2002
AUTHOR UNKNOWN, The 2001 International Technology Roadmap for Semiconductors (), 2000
Export
Markieren/ Markierung löschen
Markierte Publikationen
Web of Science
Dieser Datensatz im Web of Science®Quellen
PMID: 18244564
PubMed | Europe PMC
Suchen in