A Massively Parallel Architecture for Self-Organizing Feature Maps
Porrmann M, Witkowski U, Rückert U (2003)
IEEE Transactions on Neural Networks, Special Issue on Hardware Implementations 14(5): 1110-1121.
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Abstract / Bemerkung
A hardware accelerator for self-organizing feature maps is presented. We have developed a massively parallel architecture that, on the one hand, allows a resource-efficient implementation of small or medium-sized maps for embedded applications, requiring only small areas of silicon. On the other hand, large maps can be simulated with systems that consist of several integrated circuits that work in parallel. Apart from the learning and recall of self-organizing feature maps, the hardware accelerates data pre- and postprocessing. For the verification of our architectural concepts in a real-world environment, we have implemented an ASIC that is integrated into our heterogeneous multiprocessor system for neural applications. The performance of our system is analyzed for various simulation parameters. Additionally, the performance that can be achieved with future microelectronic technologies is estimated.
Erscheinungsjahr
2003
Zeitschriftentitel
IEEE Transactions on Neural Networks, Special Issue on Hardware Implementations
Band
14
Ausgabe
5
Seite(n)
1110-1121
ISSN
1045-9227
Page URI
https://pub.uni-bielefeld.de/record/2145324
Zitieren
Porrmann M, Witkowski U, Rückert U. A Massively Parallel Architecture for Self-Organizing Feature Maps. IEEE Transactions on Neural Networks, Special Issue on Hardware Implementations. 2003;14(5):1110-1121.
Porrmann, M., Witkowski, U., & Rückert, U. (2003). A Massively Parallel Architecture for Self-Organizing Feature Maps. IEEE Transactions on Neural Networks, Special Issue on Hardware Implementations, 14(5), 1110-1121. https://doi.org/10.1109/TNN.2003.816368
Porrmann, Mario, Witkowski, Ulf, and Rückert, Ulrich. 2003. “A Massively Parallel Architecture for Self-Organizing Feature Maps”. IEEE Transactions on Neural Networks, Special Issue on Hardware Implementations 14 (5): 1110-1121.
Porrmann, M., Witkowski, U., and Rückert, U. (2003). A Massively Parallel Architecture for Self-Organizing Feature Maps. IEEE Transactions on Neural Networks, Special Issue on Hardware Implementations 14, 1110-1121.
Porrmann, M., Witkowski, U., & Rückert, U., 2003. A Massively Parallel Architecture for Self-Organizing Feature Maps. IEEE Transactions on Neural Networks, Special Issue on Hardware Implementations, 14(5), p 1110-1121.
M. Porrmann, U. Witkowski, and U. Rückert, “A Massively Parallel Architecture for Self-Organizing Feature Maps”, IEEE Transactions on Neural Networks, Special Issue on Hardware Implementations, vol. 14, 2003, pp. 1110-1121.
Porrmann, M., Witkowski, U., Rückert, U.: A Massively Parallel Architecture for Self-Organizing Feature Maps. IEEE Transactions on Neural Networks, Special Issue on Hardware Implementations. 14, 1110-1121 (2003).
Porrmann, Mario, Witkowski, Ulf, and Rückert, Ulrich. “A Massively Parallel Architecture for Self-Organizing Feature Maps”. IEEE Transactions on Neural Networks, Special Issue on Hardware Implementations 14.5 (2003): 1110-1121.
4 Zitationen in Europe PMC
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A Novel Hardware Systolic Architecture of a Self-Organizing Map Neural Network.
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Improved Learning Performance of Hardware Self-Organizing Map Using a Novel Neighborhood Function.
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