Asynchronous network-on-chips (NoCs) for resource efficient many core architectures
Ax J, Kucza N, Porrmann M, Rückert U, Jungeblut T (2019)
In: Asynchronous Circuit Applications. Di J, Smith SC (Eds); Institution of Engineering and Technology (IET): 173-197.
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Autor*in
Herausgeber*in
Di, Jia;
Smith, Scott C.
Einrichtung
Abstract / Bemerkung
In this chapter, different GALS approaches for the implementation of embedded NoC architectures were presented. The GALS approach allows for the reduction of the resource requirements at an increased scalability of the NoC without sacrificing performance. The three approaches of synchronous, mesochronous, and asynchronous NoCs were compared. For the mesochronous NoC special synchronizers between the links were implemented. For the asynchronous NoC, the routers were completely realized as an asynchronous circuits. The results have shown that modern design methods (CCOpt design fl ow) allow a good scaling of MPSoCs even for synchronous NoCs. Nevertheless, the asynchronous NoC showed lower area and energy requirement compared to the mesochronous and synchronous implementation, while still providing a comparable performance. When comparing a place and route of an MPSoC, the asynchronous NoC leads to 3.1% less area requirements. The power consumption of an asynchronous router is only 22.4% (0.94 mW in idle state) or 53% (3.94 mW during communication) of the power consumption of a clock -based router. In the last section of the chapter, the global clock tree for an MPSoC with 256 CPUs was examined. The synchronous and mesochronous NoC show almost the same power consumption of about 7.7 mW. Using the asynchronous NoC reduces the power consumption by about 25% (5.78 mW). In addition, the mesochronous and asynchronous variants achieve a 2.6% higher clock frequency.
Erscheinungsjahr
2019
Buchtitel
Asynchronous Circuit Applications
Seite(n)
173-197
ISBN
9781785618178
eISBN
9781785618185
Page URI
https://pub.uni-bielefeld.de/record/2979460
Zitieren
Ax J, Kucza N, Porrmann M, Rückert U, Jungeblut T. Asynchronous network-on-chips (NoCs) for resource efficient many core architectures. In: Di J, Smith SC, eds. Asynchronous Circuit Applications. Institution of Engineering and Technology (IET); 2019: 173-197.
Ax, J., Kucza, N., Porrmann, M., Rückert, U., & Jungeblut, T. (2019). Asynchronous network-on-chips (NoCs) for resource efficient many core architectures. In J. Di & S. C. Smith (Eds.), Asynchronous Circuit Applications (pp. 173-197). Institution of Engineering and Technology (IET). https://doi.org/10.1049/PBCS061E_ch8
Ax, Johannes, Kucza, Nils, Porrmann, Mario, Rückert, Ulrich, and Jungeblut, Thorsten. 2019. “Asynchronous network-on-chips (NoCs) for resource efficient many core architectures”. In Asynchronous Circuit Applications, ed. Jia Di and Scott C. Smith, 173-197. Institution of Engineering and Technology (IET).
Ax, J., Kucza, N., Porrmann, M., Rückert, U., and Jungeblut, T. (2019). “Asynchronous network-on-chips (NoCs) for resource efficient many core architectures” in Asynchronous Circuit Applications, Di, J., and Smith, S. C. eds. (Institution of Engineering and Technology (IET), 173-197.
Ax, J., et al., 2019. Asynchronous network-on-chips (NoCs) for resource efficient many core architectures. In J. Di & S. C. Smith, eds. Asynchronous Circuit Applications. Institution of Engineering and Technology (IET), pp. 173-197.
J. Ax, et al., “Asynchronous network-on-chips (NoCs) for resource efficient many core architectures”, Asynchronous Circuit Applications, J. Di and S.C. Smith, eds., Institution of Engineering and Technology (IET), 2019, pp.173-197.
Ax, J., Kucza, N., Porrmann, M., Rückert, U., Jungeblut, T.: Asynchronous network-on-chips (NoCs) for resource efficient many core architectures. In: Di, J. and Smith, S.C. (eds.) Asynchronous Circuit Applications. p. 173-197. Institution of Engineering and Technology (IET) (2019).
Ax, Johannes, Kucza, Nils, Porrmann, Mario, Rückert, Ulrich, and Jungeblut, Thorsten. “Asynchronous network-on-chips (NoCs) for resource efficient many core architectures”. Asynchronous Circuit Applications. Ed. Jia Di and Scott C. Smith. Institution of Engineering and Technology (IET), 2019. 173-197.
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