Evaluation of on-chip interfaces for dynamically reconfigurable coprocessors
Griese B, Kettelhoit B, Porrmann M (2006)
In: Proceedings of the 5th International Symposium on Parallel Computing in Electrical Engineering. IEEE Computer Society. Technical Committee on Parallel Processing, Institute of Electrical and Electronics Engineers. Poland Section (Eds); Los Alamitos, Calif. : IEEE: 214-219.
Konferenzbeitrag
| Veröffentlicht | Englisch
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Autor*in
Griese, Björn;
Kettelhoit, Boris;
Porrmann, MarioUniBi 
herausgebende Körperschaft
IEEE Computer Society. Technical Committee on Parallel Processing;
Institute of Electrical and Electronics Engineers. Poland Section
Abstract / Bemerkung
Dynamically reconfigurable FPGAs are well known to combine the flexibility of software with the performance of application specific hardware. As such they can be used as powerful but still flexible coprocessors in embedded processor systems. In this paper we analyze different variants for interfacing reconfigurable hardware from an embedded processor. We describe three different on-chip buses and evaluate their usability for dynamically reconfigurable systems. In addition, we analyze the communication latencies and the speed-up factor of a hardware accelerator for floating point operations for a total of eight different coupling variants
Erscheinungsjahr
2006
Titel des Konferenzbandes
Proceedings of the 5th International Symposium on Parallel Computing in Electrical Engineering
Seite(n)
214-219
Konferenzort
Bialystok, Poland
Konferenzdatum
September 13 - 17
ISBN
0769525547
Page URI
https://pub.uni-bielefeld.de/record/2494374
Zitieren
Griese B, Kettelhoit B, Porrmann M. Evaluation of on-chip interfaces for dynamically reconfigurable coprocessors. In: IEEE Computer Society. Technical Committee on Parallel Processing, Institute of Electrical and Electronics Engineers. Poland Section, eds. Proceedings of the 5th International Symposium on Parallel Computing in Electrical Engineering. Los Alamitos, Calif. : IEEE; 2006: 214-219.
Griese, B., Kettelhoit, B., & Porrmann, M. (2006). Evaluation of on-chip interfaces for dynamically reconfigurable coprocessors. In IEEE Computer Society. Technical Committee on Parallel Processing & Institute of Electrical and Electronics Engineers. Poland Section (Eds.), Proceedings of the 5th International Symposium on Parallel Computing in Electrical Engineering (pp. 214-219). Los Alamitos, Calif. : IEEE. doi:10.1109/PARELEC.2006.36
Griese, Björn, Kettelhoit, Boris, and Porrmann, Mario. 2006. “Evaluation of on-chip interfaces for dynamically reconfigurable coprocessors”. In Proceedings of the 5th International Symposium on Parallel Computing in Electrical Engineering, ed. IEEE Computer Society. Technical Committee on Parallel Processing and Institute of Electrical and Electronics Engineers. Poland Section, 214-219. Los Alamitos, Calif. : IEEE.
Griese, B., Kettelhoit, B., and Porrmann, M. (2006). “Evaluation of on-chip interfaces for dynamically reconfigurable coprocessors” in Proceedings of the 5th International Symposium on Parallel Computing in Electrical Engineering, IEEE Computer Society. Technical Committee on Parallel Processing, and Institute of Electrical and Electronics Engineers. Poland Section eds. (Los Alamitos, Calif. : IEEE), 214-219.
Griese, B., Kettelhoit, B., & Porrmann, M., 2006. Evaluation of on-chip interfaces for dynamically reconfigurable coprocessors. In IEEE Computer Society. Technical Committee on Parallel Processing & Institute of Electrical and Electronics Engineers. Poland Section, eds. Proceedings of the 5th International Symposium on Parallel Computing in Electrical Engineering. Los Alamitos, Calif. : IEEE, pp. 214-219.
B. Griese, B. Kettelhoit, and M. Porrmann, “Evaluation of on-chip interfaces for dynamically reconfigurable coprocessors”, Proceedings of the 5th International Symposium on Parallel Computing in Electrical Engineering, IEEE Computer Society. Technical Committee on Parallel Processing and Institute of Electrical and Electronics Engineers. Poland Section, eds., Los Alamitos, Calif. : IEEE, 2006, pp.214-219.
Griese, B., Kettelhoit, B., Porrmann, M.: Evaluation of on-chip interfaces for dynamically reconfigurable coprocessors. In: IEEE Computer Society. Technical Committee on Parallel Processing and Institute of Electrical and Electronics Engineers. Poland Section (eds.) Proceedings of the 5th International Symposium on Parallel Computing in Electrical Engineering. p. 214-219. IEEE, Los Alamitos, Calif. (2006).
Griese, Björn, Kettelhoit, Boris, and Porrmann, Mario. “Evaluation of on-chip interfaces for dynamically reconfigurable coprocessors”. Proceedings of the 5th International Symposium on Parallel Computing in Electrical Engineering. Ed. IEEE Computer Society. Technical Committee on Parallel Processing and Institute of Electrical and Electronics Engineers. Poland Section. Los Alamitos, Calif. : IEEE, 2006. 214-219.
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