A Layer Model for Systematically Designing Dynamically Reconfigurable Systems
Kettelhoit B, Porrmann M (2006)
In: Proceedings of the 16th International Conference on Field Programmable Logic and Applications. IEEE Circuits and Systems Society, Escuela Politécnica Superior (Madrid) (Eds); Piscataway, NJ: IEEE: 547-552.
Konferenzbeitrag
| Veröffentlicht | Englisch
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Autor*in
Kettelhoit, Boris;
Porrmann, MarioUniBi 
herausgebende Körperschaft
IEEE Circuits and Systems Society;
Escuela Politécnica Superior (Madrid)
Abstract / Bemerkung
Partial and dynamic reconfiguration significantly enhances the potential of FPGAs, which has been shown in various prototypic implementations in the past. In this paper the authors introduce a new methodology that eases the design of dynamically reconfigurable systems. It is based on a layer model that systematically abstracts from the underlying reconfigurable hardware to the application that wants to use a dynamically loaded hardware module. With six specified layers and well defined interfaces between these layers we reduce the error-proneness of the system design while increasing the reusability of existing system components. The authors demonstrate the benefits of this design methodology with two example designs: a system-on-chip implementation and a multi-FPGA approach.
Erscheinungsjahr
2006
Titel des Konferenzbandes
Proceedings of the 16th International Conference on Field Programmable Logic and Applications
Seite(n)
547-552
Konferenzort
Madris, Spain
Konferenzdatum
August 28 - 30
ISBN
142440312X
Page URI
https://pub.uni-bielefeld.de/record/2494364
Zitieren
Kettelhoit B, Porrmann M. A Layer Model for Systematically Designing Dynamically Reconfigurable Systems. In: IEEE Circuits and Systems Society, Escuela Politécnica Superior (Madrid), eds. Proceedings of the 16th International Conference on Field Programmable Logic and Applications. Piscataway, NJ: IEEE; 2006: 547-552.
Kettelhoit, B., & Porrmann, M. (2006). A Layer Model for Systematically Designing Dynamically Reconfigurable Systems. In IEEE Circuits and Systems Society & Escuela Politécnica Superior (Madrid) (Eds.), Proceedings of the 16th International Conference on Field Programmable Logic and Applications (pp. 547-552). Piscataway, NJ: IEEE. doi:10.1109/FPL.2006.311265
Kettelhoit, Boris, and Porrmann, Mario. 2006. “A Layer Model for Systematically Designing Dynamically Reconfigurable Systems”. In Proceedings of the 16th International Conference on Field Programmable Logic and Applications, ed. IEEE Circuits and Systems Society and Escuela Politécnica Superior (Madrid), 547-552. Piscataway, NJ: IEEE.
Kettelhoit, B., and Porrmann, M. (2006). “A Layer Model for Systematically Designing Dynamically Reconfigurable Systems” in Proceedings of the 16th International Conference on Field Programmable Logic and Applications, IEEE Circuits and Systems Society, and Escuela Politécnica Superior (Madrid) eds. (Piscataway, NJ: IEEE), 547-552.
Kettelhoit, B., & Porrmann, M., 2006. A Layer Model for Systematically Designing Dynamically Reconfigurable Systems. In IEEE Circuits and Systems Society & Escuela Politécnica Superior (Madrid), eds. Proceedings of the 16th International Conference on Field Programmable Logic and Applications. Piscataway, NJ: IEEE, pp. 547-552.
B. Kettelhoit and M. Porrmann, “A Layer Model for Systematically Designing Dynamically Reconfigurable Systems”, Proceedings of the 16th International Conference on Field Programmable Logic and Applications, IEEE Circuits and Systems Society and Escuela Politécnica Superior (Madrid), eds., Piscataway, NJ: IEEE, 2006, pp.547-552.
Kettelhoit, B., Porrmann, M.: A Layer Model for Systematically Designing Dynamically Reconfigurable Systems. In: IEEE Circuits and Systems Society and Escuela Politécnica Superior (Madrid) (eds.) Proceedings of the 16th International Conference on Field Programmable Logic and Applications. p. 547-552. IEEE, Piscataway, NJ (2006).
Kettelhoit, Boris, and Porrmann, Mario. “A Layer Model for Systematically Designing Dynamically Reconfigurable Systems”. Proceedings of the 16th International Conference on Field Programmable Logic and Applications. Ed. IEEE Circuits and Systems Society and Escuela Politécnica Superior (Madrid). Piscataway, NJ: IEEE, 2006. 547-552.
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