Multiobjective optimization for transistor sizing sub-threshold CMOSlogic standard cells
Blesken M, Lütkemeier S, Rückert U (2010)
In: Proc. IEEE Int Circuits and Systems (ISCAS) Symp. Institute of Electrical and Electronics Engineers (Ed); Piscataway, NJ: IEEE: 1480-1483.
Konferenzbeitrag
| Veröffentlicht | Englisch
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Autor*in
Blesken, M.;
Lütkemeier, SvenUniBi;
Rückert, UlrichUniBi
herausgebende Körperschaft
Institute of Electrical and Electronics Engineers
Abstract / Bemerkung
Transistor sizing of sub-threshold standard cells for digital ultra-low power systems is a very challenging task because robustness has to be considered as an important design objective in addition to the competing resources power consumption and propagation delay. In this paper we regard this task as a multiobjective optimization problem (MOP) and show that the support of MOP algorithms is necessary and beneficial in the design process of sub-threshold CMOS logic standard cells. Optimization results are presented for an inverter, NAND gate, and NOR gate in a 65 nm process technology.
Erscheinungsjahr
2010
Titel des Konferenzbandes
Proc. IEEE Int Circuits and Systems (ISCAS) Symp
Seite(n)
1480-1483
ISBN
9781424453085
Page URI
https://pub.uni-bielefeld.de/record/2475069
Zitieren
Blesken M, Lütkemeier S, Rückert U. Multiobjective optimization for transistor sizing sub-threshold CMOSlogic standard cells. In: Institute of Electrical and Electronics Engineers, ed. Proc. IEEE Int Circuits and Systems (ISCAS) Symp. Piscataway, NJ: IEEE; 2010: 1480-1483.
Blesken, M., Lütkemeier, S., & Rückert, U. (2010). Multiobjective optimization for transistor sizing sub-threshold CMOSlogic standard cells. In Institute of Electrical and Electronics Engineers (Ed.), Proc. IEEE Int Circuits and Systems (ISCAS) Symp (pp. 1480-1483). Piscataway, NJ: IEEE. doi:10.1109/ISCAS.2010.5537349
Blesken, M., Lütkemeier, Sven, and Rückert, Ulrich. 2010. “Multiobjective optimization for transistor sizing sub-threshold CMOSlogic standard cells”. In Proc. IEEE Int Circuits and Systems (ISCAS) Symp, ed. Institute of Electrical and Electronics Engineers, 1480-1483. Piscataway, NJ: IEEE.
Blesken, M., Lütkemeier, S., and Rückert, U. (2010). “Multiobjective optimization for transistor sizing sub-threshold CMOSlogic standard cells” in Proc. IEEE Int Circuits and Systems (ISCAS) Symp, Institute of Electrical and Electronics Engineers ed. (Piscataway, NJ: IEEE), 1480-1483.
Blesken, M., Lütkemeier, S., & Rückert, U., 2010. Multiobjective optimization for transistor sizing sub-threshold CMOSlogic standard cells. In Institute of Electrical and Electronics Engineers, ed. Proc. IEEE Int Circuits and Systems (ISCAS) Symp. Piscataway, NJ: IEEE, pp. 1480-1483.
M. Blesken, S. Lütkemeier, and U. Rückert, “Multiobjective optimization for transistor sizing sub-threshold CMOSlogic standard cells”, Proc. IEEE Int Circuits and Systems (ISCAS) Symp, Institute of Electrical and Electronics Engineers, ed., Piscataway, NJ: IEEE, 2010, pp.1480-1483.
Blesken, M., Lütkemeier, S., Rückert, U.: Multiobjective optimization for transistor sizing sub-threshold CMOSlogic standard cells. In: Institute of Electrical and Electronics Engineers (ed.) Proc. IEEE Int Circuits and Systems (ISCAS) Symp. p. 1480-1483. IEEE, Piscataway, NJ (2010).
Blesken, M., Lütkemeier, Sven, and Rückert, Ulrich. “Multiobjective optimization for transistor sizing sub-threshold CMOSlogic standard cells”. Proc. IEEE Int Circuits and Systems (ISCAS) Symp. Ed. Institute of Electrical and Electronics Engineers. Piscataway, NJ: IEEE, 2010. 1480-1483.
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