Dynamically reconfigurable system-on-programmable-chip
Kalte H, Langen D, Vonnahme E, Brinkmann A, Rückert U (2002)
In: Parallel, Distributed and Network-based Processing, 2002. Proceedings. 10th Euromicro Workshop on. IEEE Comput. Soc: 235-242.
Konferenzbeitrag
| Veröffentlicht | Englisch
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Autor*in
Kalte, H.;
Langen, D.;
Vonnahme, E.;
Brinkmann, A.;
Rückert, UlrichUniBi
Abstract / Bemerkung
Today’s high-density FPGAs and intellectual property
(IP) components enable the integration of complex systems
in one programmable chip. New design strategies
and concepts have to be developed in order to utilize the
new system-level integration facilities. The approach
introduced within this paper describes the implementation
of a communication infrastructure that provides a number
of on-chip IP-sockets. By using the FPGA-feature of partial
dynamic reconfiguration, different IP components can
be plugged into these sockets during runtime. This leads
to a reconfigurable system that can be adapted to varying
demands. In this context we designed a 32-bit RISC processor
and an AMBA on-chip interconnection bus. Finally
we mapped these components on a reconfigurable systemlevel
FPGA. The resulting sizes and the utilization of the
FPGA’s resources are presented within the last part of
this paper.
Stichworte
system-on-programmable-chip;
application specific integrated circuits;
plug-in components;
system-level integration facilities;
on-chip IP-sockets;
partial dynamic reconfiguration;
reconfigurable system-level FPGA;
intellectual property components;
hardware size;
high-density FPGA;
complex systems integration;
dynamically reconfigurable system;
communication infrastructure;
FPGA resource utilization;
chip design strategies;
reduced instruction set computing;
RISC processor;
Advanced Microcontroller Bus Architecture;
32 bit;
AMBA on-chip interconnection bus;
field programmable gate arrays;
industrial property;
reconfigurable architectures;
microprocessor chips;
system buses
Erscheinungsjahr
2002
Titel des Konferenzbandes
Parallel, Distributed and Network-based Processing, 2002. Proceedings. 10th Euromicro Workshop on
Seite(n)
235-242
ISBN
0769514448
Page URI
https://pub.uni-bielefeld.de/record/2286322
Zitieren
Kalte H, Langen D, Vonnahme E, Brinkmann A, Rückert U. Dynamically reconfigurable system-on-programmable-chip. In: Parallel, Distributed and Network-based Processing, 2002. Proceedings. 10th Euromicro Workshop on. IEEE Comput. Soc; 2002: 235-242.
Kalte, H., Langen, D., Vonnahme, E., Brinkmann, A., & Rückert, U. (2002). Dynamically reconfigurable system-on-programmable-chip. Parallel, Distributed and Network-based Processing, 2002. Proceedings. 10th Euromicro Workshop on, 235-242. IEEE Comput. Soc. https://doi.org/10.1109/EMPDP.2002.994277
Kalte, H., Langen, D., Vonnahme, E., Brinkmann, A., and Rückert, Ulrich. 2002. “Dynamically reconfigurable system-on-programmable-chip”. In Parallel, Distributed and Network-based Processing, 2002. Proceedings. 10th Euromicro Workshop on, 235-242. IEEE Comput. Soc.
Kalte, H., Langen, D., Vonnahme, E., Brinkmann, A., and Rückert, U. (2002). “Dynamically reconfigurable system-on-programmable-chip” in Parallel, Distributed and Network-based Processing, 2002. Proceedings. 10th Euromicro Workshop on (IEEE Comput. Soc), 235-242.
Kalte, H., et al., 2002. Dynamically reconfigurable system-on-programmable-chip. In Parallel, Distributed and Network-based Processing, 2002. Proceedings. 10th Euromicro Workshop on. IEEE Comput. Soc, pp. 235-242.
H. Kalte, et al., “Dynamically reconfigurable system-on-programmable-chip”, Parallel, Distributed and Network-based Processing, 2002. Proceedings. 10th Euromicro Workshop on, IEEE Comput. Soc, 2002, pp.235-242.
Kalte, H., Langen, D., Vonnahme, E., Brinkmann, A., Rückert, U.: Dynamically reconfigurable system-on-programmable-chip. Parallel, Distributed and Network-based Processing, 2002. Proceedings. 10th Euromicro Workshop on. p. 235-242. IEEE Comput. Soc (2002).
Kalte, H., Langen, D., Vonnahme, E., Brinkmann, A., and Rückert, Ulrich. “Dynamically reconfigurable system-on-programmable-chip”. Parallel, Distributed and Network-based Processing, 2002. Proceedings. 10th Euromicro Workshop on. IEEE Comput. Soc, 2002. 235-242.
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