Multiobjective optimization for transistor sizing of CMOS logic standard cells using set-oriented numerical techniques

Blesken M, Rückert U, Steenken D, Witting K, Dellnitz M (2009)
In: NORCHIP, 2009. Institute of Electrical and Electronics Engineers (Ed); Piscataway, NJ: IEEE: 1-4.

Konferenzbeitrag | Veröffentlicht | Englisch
 
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Autor*in
Blesken, Matthias; Rückert, UlrichUniBi; Steenken, Dominik; Witting, Katrin; Dellnitz, Michael
herausgebende Körperschaft
Institute of Electrical and Electronics Engineers
Abstract / Bemerkung
The design of resource efficient integrated circuits (IC) requires solving a minimization problem of more than one objective given as measures of available resources. This multiobjective optimization problem (MOP) can be solved on the smallest unit, the standard cells, to improve the performance of the entire IC. The traditional way of sizing the transistors of a standard logic cell does not focus on the resources directly. In this work transistor sizing is approached via an MOP and solved by set-oriented numerical techniques. A comparison of the Pareto optimal designs to elements of a commercial standard cell library indicates that for some gates the performance can even be significantly improved.
Stichworte
CMOS logic standard cells; integrated circuits design; logic design; transistors; Pareto optimal designs; integrated circuit design; transistor sizing; multiobjective optimization; CMOS logic circuits
Erscheinungsjahr
2009
Titel des Konferenzbandes
NORCHIP, 2009
Seite(n)
1-4
Konferenz
NORCHIP 2009
Konferenzort
Trondheim, Norway
Konferenzdatum
2009-11-16 – 2009-11-17
ISBN
978-1-4244-4310-9
eISBN
978-1-4244-4311-6
Page URI
https://pub.uni-bielefeld.de/record/2286299

Zitieren

Blesken M, Rückert U, Steenken D, Witting K, Dellnitz M. Multiobjective optimization for transistor sizing of CMOS logic standard cells using set-oriented numerical techniques. In: Institute of Electrical and Electronics Engineers, ed. NORCHIP, 2009. Piscataway, NJ: IEEE; 2009: 1-4.
Blesken, M., Rückert, U., Steenken, D., Witting, K., & Dellnitz, M. (2009). Multiobjective optimization for transistor sizing of CMOS logic standard cells using set-oriented numerical techniques. In Institute of Electrical and Electronics Engineers (Ed.), NORCHIP, 2009 (pp. 1-4). Piscataway, NJ: IEEE. https://doi.org/10.1109/NORCHP.2009.5397800
Blesken, M., Rückert, U., Steenken, D., Witting, K., and Dellnitz, M. (2009). “Multiobjective optimization for transistor sizing of CMOS logic standard cells using set-oriented numerical techniques” in NORCHIP, 2009, Institute of Electrical and Electronics Engineers ed. (Piscataway, NJ: IEEE), 1-4.
Blesken, M., et al., 2009. Multiobjective optimization for transistor sizing of CMOS logic standard cells using set-oriented numerical techniques. In Institute of Electrical and Electronics Engineers, ed. NORCHIP, 2009. Piscataway, NJ: IEEE, pp. 1-4.
M. Blesken, et al., “Multiobjective optimization for transistor sizing of CMOS logic standard cells using set-oriented numerical techniques”, NORCHIP, 2009, Institute of Electrical and Electronics Engineers, ed., Piscataway, NJ: IEEE, 2009, pp.1-4.
Blesken, M., Rückert, U., Steenken, D., Witting, K., Dellnitz, M.: Multiobjective optimization for transistor sizing of CMOS logic standard cells using set-oriented numerical techniques. In: Institute of Electrical and Electronics Engineers (ed.) NORCHIP, 2009. p. 1-4. IEEE, Piscataway, NJ (2009).
Blesken, Matthias, Rückert, Ulrich, Steenken, Dominik, Witting, Katrin, and Dellnitz, Michael. “Multiobjective optimization for transistor sizing of CMOS logic standard cells using set-oriented numerical techniques”. NORCHIP, 2009. Ed. Institute of Electrical and Electronics Engineers. Piscataway, NJ: IEEE, 2009. 1-4.

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