PUB - Publikationen an der Universität Bielefeld

The integrated circuit scale integration evolution in the last sixty years has today enabled the design of highly complex digital systems on a single semiconductor chip. Due to the great cost of semiconductor chip projects, ensuring these digital systems work first-time is paramount. Digital verification paradigms and techniques have therefore also evolved in parallel with the scale integration evolution. Today the most prevalent paradigm for digital designs modelled at the Register Transfer Logic (RTL) level is the ‘simulation based constrained random coverage driven functional verification’. This paradigm is abbreviated as CFV in this research. While greatly enhancing the verification process for the bulk of the RTL design, reaching full functional coverage, a necessary step for verification closure, remains a major bottleneck, mainly due to the manual intervention in the process. The present research tackles this issue by exploring the use and the integration of deep reinforcement learning techniques in a CFV environment. The research makes use of a deep learning approach to a Q-Learning variant, the same approach as used in the work by DeepMind Technologies to play Atari games. The RTL design used throughout the research is an LZW encoder as it is on one hand sufficiently complex to be representative, and on the other hand, it allows for an unambiguous assessment of the novel approach on the functional coverage closure process. I show that the use and integration of deep Q-Learning based techniques in a CFV environment is greatly beneficial in generating scenarios targeting functional coverage holes. It also allows for the complete automation of the functional coverage closure process for the LZW encoder, paving the way to broaden its use during the verification of semiconductor projects.