Multilevel process on large area wafers for nanoscale devices

Pires BJ, Silva AV, Moskaltsova A, Deepak FL, Brogueira P, Leitao DC, Cardoso S (2018)
JOURNAL OF MANUFACTURING PROCESSES 32: 222-229.

Zeitschriftenaufsatz | Veröffentlicht | Englisch
 
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Autor*in
Pires, B. J.; Silva, A. V.; Moskaltsova, AnastasiiaUniBi; Deepak, F. L.; Brogueira, P.; Leitao, D. C.; Cardoso, S.
Abstract / Bemerkung
Spintronic nanodevices are consolidating a highly reputed position in advanced manufacturing industry, not only due to progresses in magnetic hard disk sensors, but also the memory market. The ability to integrate magnetic thin films on large area wafers and subsequent nanofabrication into functional devices is key for such success. This work describes methodologies used for definition of sub-100 nm pillars, using reliable via opening to contact nanopillars buried in a dielectric film. A two consecutive step electron beam lithography process is used to fabricate current-perpendicular-to plane nanodevices. The first step is required to pattern nanopillars down to 30 nm. The second provides access to nanopillar top through nanovias definition and reactive ion etching. Optimum alignment of multilevel exposures ensures the most accurate positioning in the shortest time. Most importantly, the results are obtained on 150 mm diameter wafers, where additional challenges of uniformity of resists, oxides and metals are critical for end-point control and improved yield of fabricated devices. The design of customized test structures allowed control of etching end-point. (C) 2018 The Society of Manufacturing Engineers. Published by Elsevier Ltd. All rights reserved.
Stichworte
Nanofabrication; Electron beam lithography; Reactive ion etching; Metrology
Erscheinungsjahr
2018
Zeitschriftentitel
JOURNAL OF MANUFACTURING PROCESSES
Band
32
Seite(n)
222-229
ISSN
1526-6125
Page URI
https://pub.uni-bielefeld.de/record/2921242

Zitieren

Pires BJ, Silva AV, Moskaltsova A, et al. Multilevel process on large area wafers for nanoscale devices. JOURNAL OF MANUFACTURING PROCESSES. 2018;32:222-229.
Pires, B. J., Silva, A. V., Moskaltsova, A., Deepak, F. L., Brogueira, P., Leitao, D. C., & Cardoso, S. (2018). Multilevel process on large area wafers for nanoscale devices. JOURNAL OF MANUFACTURING PROCESSES, 32, 222-229. doi:10.1016/j.jmapro.2018.01.024
Pires, B. J., Silva, A. V., Moskaltsova, A., Deepak, F. L., Brogueira, P., Leitao, D. C., and Cardoso, S. (2018). Multilevel process on large area wafers for nanoscale devices. JOURNAL OF MANUFACTURING PROCESSES 32, 222-229.
Pires, B.J., et al., 2018. Multilevel process on large area wafers for nanoscale devices. JOURNAL OF MANUFACTURING PROCESSES, 32, p 222-229.
B.J. Pires, et al., “Multilevel process on large area wafers for nanoscale devices”, JOURNAL OF MANUFACTURING PROCESSES, vol. 32, 2018, pp. 222-229.
Pires, B.J., Silva, A.V., Moskaltsova, A., Deepak, F.L., Brogueira, P., Leitao, D.C., Cardoso, S.: Multilevel process on large area wafers for nanoscale devices. JOURNAL OF MANUFACTURING PROCESSES. 32, 222-229 (2018).
Pires, B. J., Silva, A. V., Moskaltsova, Anastasiia, Deepak, F. L., Brogueira, P., Leitao, D. C., and Cardoso, S. “Multilevel process on large area wafers for nanoscale devices”. JOURNAL OF MANUFACTURING PROCESSES 32 (2018): 222-229.

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