Boris Hübener
PEVZ-ID
4 Publikationen
-
2016 | Bielefelder E-Dissertation | PUB-ID: 2906927Analyse verschiedener Architekturvarianten des CoreVA-VLIW-ProzessorsPUB | PDF
Hübener, Boris, Analyse verschiedener Architekturvarianten des CoreVA-VLIW-Prozessors. (). Bielefeld, 2016 -
2014 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2698929CoreVA: A Configurable Resource-efficient VLIW Processor ArchitecturePUB | DOI
Hübener, Boris, CoreVA: A Configurable Resource-efficient VLIW Processor Architecture. Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing (). , 2014 -
2013 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2634614A Systematic Approach for Optimized Bypass Configurations for Application-specific Embedded ProcessorsPUB | DOI | Download (ext.) | WoS
Jungeblut, Thorsten, A Systematic Approach for Optimized Bypass Configurations for Application-specific Embedded Processors. ACM Trans. Embed. Comput. Syst. 13 (2). , 2013 -
2011 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2476993Resource Efficiency of Scalable Processor Architectures for SDR-based Applications (Invited)PUB | Dateien verfügbar
Jungeblut, Thorsten, Resource Efficiency of Scalable Processor Architectures for SDR-based Applications (Invited). Proc. of the Radar, Communication and Measurement Conference (RADCOM) (). , 2011