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23 Publikationen

2018 | Kurzbeitrag Konferenz / Poster | Veröffentlicht | PUB-ID: 2918788 OA
Accelerating Hamming Distance Comparisons for Locality Sensitive Hashing (LSH) using FPGAs
Kaiser, Martin, Accelerating Hamming Distance Comparisons for Locality Sensitive Hashing (LSH) using FPGAs. 12th CeBiTec Symposium - Big Data in Medicine and Biotechnology - Abstract Book 12 (). Bielefeld, 2018
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2016 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2900943
Comparison of Acceleration Techniques for Selected Low-Level Bioinformatics Operations
Langenkämper, Daniel, Comparison of Acceleration Techniques for Selected Low-Level Bioinformatics Operations. Frontiers in Genetics 7 (). , 2016
PUB | DOI | WoS | PubMed | Europe PMC
 
2015 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2901107
A resource-efficient multi-camera GigE vision IP core for embedded vision processing platforms
Ibraheem, Omar Waleed, A resource-efficient multi-camera GigE vision IP core for embedded vision processing platforms. ReConFigurable Computing and FPGAs (ReConFig), 2015 International Conference on (). , 2015
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2014 | Bielefelder E-Dissertation | PUB-ID: 2652142 OA
Ressourceneffiziente Hardware-Software-Kombinationen für Kryptographie mit elliptischen Kurven
Puttmann, Christoph, Ressourceneffiziente Hardware-Software-Kombinationen für Kryptographie mit elliptischen Kurven. (). Bielefeld, 2014
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2013 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2622226
A Novel Fault Tolerant and Runtime Reconfigurable Platform for Satellite Payload Processing
Sterpone, Luca, A Novel Fault Tolerant and Runtime Reconfigurable Platform for Satellite Payload Processing. IEEE Transactions on Computers 62 (8). , 2013
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2013 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2681304
Dynamic neutron testing of Dynamically Reconfigurable Processing Modules architecture
Sterpone, Luca, Dynamic neutron testing of Dynamically Reconfigurable Processing Modules architecture. Adaptive Hardware and Systems (AHS), 2013 NASA/ESA Conference on (). , 2013
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2012 | Bielefelder E-Dissertation | PUB-ID: 2547735 OA
Application-driven exploration of a programmable platform for Wireless LAN
Loeb, Hans-Peter, Application-driven exploration of a programmable platform for Wireless LAN. (). Bielefeld, 2012
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2012 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2559365
Optimizing inter-FPGA communication by automatic channel adaptation
Romoth, Johannes, Optimizing inter-FPGA communication by automatic channel adaptation. Reconfigurable Computing and FPGAs (ReConFig), 2012 International Conference on (). , 2012
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2012 | Bielefelder E-Dissertation | PUB-ID: 2463253 OA
Dynamically reconfigurable hardware for embedded control systems
Paiz Gatica, Carlos Vladimir, Dynamically reconfigurable hardware for embedded control systems. (). Bielefeld, 2012
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2011 | Bielefelder E-Dissertation | PUB-ID: 2407551 OA
Entwurfsraumexploration ressourceneffizienter VLIW-Prozessoren
Jungeblut, Thorsten, Entwurfsraumexploration ressourceneffizienter VLIW-Prozessoren. (). Bielefeld, 2011
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2011 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286173
Automatic HDL-Based Generation of Homogeneous Hard Macros for FPGAs
Korf, Sebastian, Automatic HDL-Based Generation of Homogeneous Hard Macros for FPGAs. Field-Programmable Custom Computing Machines (FCCM), 2011 IEEE 19th Annual International Symposium on (). , 2011
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2009 | Dissertation | PUB-ID: 1926542
Analog and Digital Hardware Implementations of Biologically Inspired Algorithms in Mobile Robotics
Köhler, Tim, Analog and Digital Hardware Implementations of Biologically Inspired Algorithms in Mobile Robotics. (). Tönning, 2009
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2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2285993
Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on Linux
Rana, V., Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on Linux. Proceedings of the 21st International Parallel and Distributed Processing Symposium (IPDPS 2007) - Reconfigurable Architecture Workshop (RAW), IEEE Computer Society. (). , 2007
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2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286362
GigaNoC - A Hierarchical Network-on-Chip for Scalable Chip-Multiprocessors
Puttmann, C., GigaNoC - A Hierarchical Network-on-Chip for Scalable Chip-Multiprocessors. Digital System Design Architectures, Methods and Tools, 2007. DSD 2007. 10th Euromicro Conference on (). , 2007
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2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286250
A Digital Framework for Pulse Coded Neural Network Hardware with Bit-Serial Operation
Kaulmann, T., A Digital Framework for Pulse Coded Neural Network Hardware with Bit-Serial Operation. Hybrid Intelligent Systems, 2007. HIS 2007. 7th International Conference on (). , 2007
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2006 | Bielefelder E-Dissertation | PUB-ID: 2306473 OA
Herstellung und Charakterisierung von Logikarrays mit ultrakleinen magnetischen Tunnelelementen
Meyners, Dirk, Herstellung und Charakterisierung von Logikarrays mit ultrakleinen magnetischen Tunnelelementen. (). Bielefeld (Germany), 2006
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2004 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286356
System-on-programmable-chip approach enabling online fine-grained 1D-placement
Kalte, H., System-on-programmable-chip approach enabling online fine-grained 1D-placement. Parallel and Distributed Processing Symposium, 2004. Proceedings. 18th International (). , 2004
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2004 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286138
gNBX - reconfigurable hardware acceleration of self-organizing maps
Pohl, C., gNBX - reconfigurable hardware acceleration of self-organizing maps. Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on (). , 2004
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2003 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 1611555
The COMPASS RICH-1 read-out system
Baum, Günter, The COMPASS RICH-1 read-out system. 502 (1). , 2003
PUB | DOI | WoS | Inspire
 
2002 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286322
Dynamically reconfigurable system-on-programmable-chip
Kalte, H., Dynamically reconfigurable system-on-programmable-chip. Parallel, Distributed and Network-based Processing, 2002. Proceedings. 10th Euromicro Workshop on (). , 2002
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