Please note that PUB no longer supports Internet Explorer versions 8 or 9 (or earlier).

We recommend upgrading to the latest Internet Explorer, Google Chrome, or Firefox.

23 Publikationen

2018 | Kurzbeitrag Konferenz / Poster | Veröffentlicht | PUB-ID: 2918788 OA
Kaiser, M., et al., 2018. Accelerating Hamming Distance Comparisons for Locality Sensitive Hashing (LSH) using FPGAs. In 12th CeBiTec Symposium - Big Data in Medicine and Biotechnology - Abstract Book. no.12 Bielefeld, pp. 48-49.
PUB | PDF
 
2016 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2900943
Langenkämper, D., et al., 2016. Comparison of Acceleration Techniques for Selected Low-Level Bioinformatics Operations. Frontiers in Genetics, 7: 5.
PUB | DOI | WoS | PubMed | Europe PMC
 
2015 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2901107
Ibraheem, O.W., et al., 2015. A resource-efficient multi-camera GigE vision IP core for embedded vision processing platforms. In ReConFigurable Computing and FPGAs (ReConFig), 2015 International Conference on. IEEE, pp. 1-6.
PUB | DOI
 
2014 | Bielefelder E-Dissertation | PUB-ID: 2652142 OA
Puttmann, C., 2014. Ressourceneffiziente Hardware-Software-Kombinationen für Kryptographie mit elliptischen Kurven, Bielefeld: Universität Bielefeld.
PUB | PDF
 
2013 | Zeitschriftenaufsatz | Veröffentlicht | PUB-ID: 2622226
Sterpone, L., Porrmann, M., & Hagemeyer, J., 2013. A Novel Fault Tolerant and Runtime Reconfigurable Platform for Satellite Payload Processing. IEEE Transactions on Computers, 62(8), p 1508-1525.
PUB | DOI | WoS
 
2013 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2681304
Sterpone, L., et al., 2013. Dynamic neutron testing of Dynamically Reconfigurable Processing Modules architecture. In Adaptive Hardware and Systems (AHS), 2013 NASA/ESA Conference on. pp. 184-188.
PUB | DOI | Download (ext.)
 
2012 | Bielefelder E-Dissertation | PUB-ID: 2547735 OA
Loeb, H.-P., 2012. Application-driven exploration of a programmable platform for Wireless LAN, Bielefeld: Universität Bielefeld.
PUB | PDF
 
2012 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2559365
Romoth, J., et al., 2012. Optimizing inter-FPGA communication by automatic channel adaptation. In Reconfigurable Computing and FPGAs (ReConFig), 2012 International Conference on. pp. 1-7.
PUB | DOI
 
2012 | Bielefelder E-Dissertation | PUB-ID: 2463253 OA
Paiz Gatica, C.V., 2012. Dynamically reconfigurable hardware for embedded control systems, Bielefeld: Universität.
PUB | PDF
 
2011 | Bielefelder E-Dissertation | PUB-ID: 2407551 OA
Jungeblut, T., 2011. Entwurfsraumexploration ressourceneffizienter VLIW-Prozessoren, Bielefeld: Universität Bielefeld.
PUB | PDF
 
2011 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286173
Korf, S., et al., 2011. Automatic HDL-Based Generation of Homogeneous Hard Macros for FPGAs. In Field-Programmable Custom Computing Machines (FCCM), 2011 IEEE 19th Annual International Symposium on. pp. 125-132.
PUB | Download (ext.)
 
2009 | Dissertation | PUB-ID: 1926542
Köhler, T., 2009. Analog and Digital Hardware Implementations of Biologically Inspired Algorithms in Mobile Robotics, Tönning: Der Andere Verlag.
PUB
 
2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2285993
Rana, V., et al., 2007. Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on Linux. In Proceedings of the 21st International Parallel and Distributed Processing Symposium (IPDPS 2007) - Reconfigurable Architecture Workshop (RAW), IEEE Computer Society.
PUB | DOI
 
2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286362
Puttmann, C., et al., 2007. GigaNoC - A Hierarchical Network-on-Chip for Scalable Chip-Multiprocessors. In Digital System Design Architectures, Methods and Tools, 2007. DSD 2007. 10th Euromicro Conference on. pp. 495-502.
PUB | Download (ext.)
 
2007 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286250
Kaulmann, T., Dikmen, D., & Rückert, U., 2007. A Digital Framework for Pulse Coded Neural Network Hardware with Bit-Serial Operation. In Hybrid Intelligent Systems, 2007. HIS 2007. 7th International Conference on. pp. 302-307.
PUB
 
2006 | Bielefelder E-Dissertation | PUB-ID: 2306473 OA
Meyners, D., 01T00:00:00Z.01.1970 Herstellung und Charakterisierung von Logikarrays mit ultrakleinen magnetischen Tunnelelementen, Bielefeld (Germany): Bielefeld University.
PUB | PDF
 
2004 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286356
Kalte, H., Porrmann, M., & Rückert, U., 2004. System-on-programmable-chip approach enabling online fine-grained 1D-placement. In Parallel and Distributed Processing Symposium, 2004. Proceedings. 18th International. pp. 141.
PUB | DOI
 
2004 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286138
Pohl, C., et al., 2004. gNBX - reconfigurable hardware acceleration of self-organizing maps. In Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on. pp. 97-104.
PUB | DOI
 
2003 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 1611555
Baum, G., et al., 2003. The COMPASS RICH-1 read-out system. Nucl.Instrum.Meth. A, 502(1), p 246-250.
PUB | DOI | WoS | Inspire
 
2002 | Konferenzbeitrag | Veröffentlicht | PUB-ID: 2286322
Kalte, H., et al., 2002. Dynamically reconfigurable system-on-programmable-chip. In Parallel, Distributed and Network-based Processing, 2002. Proceedings. 10th Euromicro Workshop on. pp. 235-242.
PUB | DOI
 

Filter und Suchbegriffe

keyword="FPGA"

Suche

Publikationen filtern

Darstellung / Sortierung

Zitationsstil: harvard1

Export / Einbettung