PUB - Publikationen an der Universität Bielefeld

Synthetic genetic logic circuits are an application of synthetic biology where biological parts of the DNA from inside a cell are engineered to implement logical functions. Such circuits exhibit a nondeterministic behavior and are much harder to characterize in contrast to electronic logic circuits. Approaches to analyzing the threshold values and timing analysis of single or cascaded genetic logic circuits have been previously proposed, however, they suffer from long latency. There is a potential for parallelizing the procedure which verifies the obtained threshold values for obtaining lower run times. In this work, we introduce a fast approach to estimating threshold values through a parallelized verification procedure. The proposed algorithm takes significantly less time than the previous approach exhibiting a time complexity of ∅(N) reduced from ∅(N 2).