Power-Efficient Estimation of Silicon Neuron Firing Rates with Floating-Gate Transistors
Nease S, Chicca E (2015)
In: 2015 European Conference on Circuit Theory and Design (ECCTD). Piscataway, NJ: IEEE: 1-4.
Konferenzbeitrag
| Veröffentlicht | Englisch
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Abstract / Bemerkung
Many subsystems in the brain require an estimate of neural activity to function properly. For example, models of neural homeostasis and synaptic plasticity incorporate these estimates. Here we present a method for estimating a neuromorphic neuron’s firing rate using floating-gate transistors. This technology allows for the long time constants required for rate estimation and homeostatic plasticity. As a neuron fires, the floating-gate’s terminals are modified such that the steady-state voltage on the floating-gate represents an estimate of the neuron’s firing rate. The primary benefits of this scheme are low power consumption and compactness.
Stichworte
Floating-Gate;
Neuromorphic
Erscheinungsjahr
2015
Titel des Konferenzbandes
2015 European Conference on Circuit Theory and Design (ECCTD)
Seite(n)
1-4
Konferenz
European conference on circuit theory and design, ECCTD
Konferenzort
Trondheim, Norway
Konferenzdatum
2015-08-26 – 2015-08-28
eISBN
978-1-4799-9877-7
Page URI
https://pub.uni-bielefeld.de/record/2757270
Zitieren
Nease S, Chicca E. Power-Efficient Estimation of Silicon Neuron Firing Rates with Floating-Gate Transistors. In: 2015 European Conference on Circuit Theory and Design (ECCTD). Piscataway, NJ: IEEE; 2015: 1-4.
Nease, S., & Chicca, E. (2015). Power-Efficient Estimation of Silicon Neuron Firing Rates with Floating-Gate Transistors. 2015 European Conference on Circuit Theory and Design (ECCTD), 1-4. Piscataway, NJ: IEEE. doi:10.1109/ECCTD.2015.7300005
Nease, Stephen, and Chicca, Elisabetta. 2015. “Power-Efficient Estimation of Silicon Neuron Firing Rates with Floating-Gate Transistors”. In 2015 European Conference on Circuit Theory and Design (ECCTD), 1-4. Piscataway, NJ: IEEE.
Nease, S., and Chicca, E. (2015). “Power-Efficient Estimation of Silicon Neuron Firing Rates with Floating-Gate Transistors” in 2015 European Conference on Circuit Theory and Design (ECCTD) (Piscataway, NJ: IEEE), 1-4.
Nease, S., & Chicca, E., 2015. Power-Efficient Estimation of Silicon Neuron Firing Rates with Floating-Gate Transistors. In 2015 European Conference on Circuit Theory and Design (ECCTD). Piscataway, NJ: IEEE, pp. 1-4.
S. Nease and E. Chicca, “Power-Efficient Estimation of Silicon Neuron Firing Rates with Floating-Gate Transistors”, 2015 European Conference on Circuit Theory and Design (ECCTD), Piscataway, NJ: IEEE, 2015, pp.1-4.
Nease, S., Chicca, E.: Power-Efficient Estimation of Silicon Neuron Firing Rates with Floating-Gate Transistors. 2015 European Conference on Circuit Theory and Design (ECCTD). p. 1-4. IEEE, Piscataway, NJ (2015).
Nease, Stephen, and Chicca, Elisabetta. “Power-Efficient Estimation of Silicon Neuron Firing Rates with Floating-Gate Transistors”. 2015 European Conference on Circuit Theory and Design (ECCTD). Piscataway, NJ: IEEE, 2015. 1-4.
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Nease_Chicca15.pdf
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