A 1.2-V analog interface for a 300-MSps HD video digitizer in Core 65-nm CMOS

Aamir SA, Angelova P, Wikner JJ (2014)
IEEE Transactions on VLSI Systems 22(4): 888-898.

Zeitschriftenaufsatz | Veröffentlicht | Englisch
 
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DOI
Autor*in
Aamir, Syed AhmedUniBi; Angelova, PolinaUniBi; Wikner, J J.
Einrichtung
Technische Fakultät
Center of Excellence - Cognitive Interaction Technology CITEC
Abstract / Bemerkung
This paper describes the front-end of a fully integrated analog interface for 300 MSps, high-definition video digitizers in a system on-chip environment. The analog interface is implemented in a 1.2 V, 65-nm digital CMOS process and the design minimizes the number of power domains using core transistors only. Each analog video receiver channel contains an integrated multiplexer with a current-mode dc-clamp, a programmable gain amplifier (PGA) and a pseudo second-order RC low-pass filter. The digital charge-pump clamp is integrated with low-voltage bootstrapped tee-switches inside the multiplexer, while restoring the dc component of ac-coupled inputs. The PGA contains a four-stage fully symmetric pseudo-differential amplifier with common-mode feedforward and inherent common-mode feedback, utilized in a closed loop capacitive feedback configuration. The amplifier features offset cancellation during the horizontal blanking. The video interface is evaluated using a unique test signal over a range of video formats for INL+/DNL+, INL-/DNL-. The 0.07-0.39 mV INL, 2-70 μV DNL, and 66-74 dB of SFDR, enable us to target various formats for 9-12 bit Low-voltage digitizers.
Stichworte
Analog-to-digital conversion (ADC); CMOS analog integrated circuits (ICs); HDTV; MOSFET switches; video AFEs; programmable gain amplifiers (PGAs)
Erscheinungsjahr
2014
Zeitschriftentitel
IEEE Transactions on VLSI Systems
Band
22
Ausgabe
4
Seite(n)
888-898
ISSN
1063-8210
eISSN
1557-9999
Page URI
https://pub.uni-bielefeld.de/record/2559683

Zitieren

Aamir SA, Angelova P, Wikner JJ. A 1.2-V analog interface for a 300-MSps HD video digitizer in Core 65-nm CMOS. IEEE Transactions on VLSI Systems. 2014;22(4):888-898.
Aamir, S. A., Angelova, P., & Wikner, J. J. (2014). A 1.2-V analog interface for a 300-MSps HD video digitizer in Core 65-nm CMOS. IEEE Transactions on VLSI Systems, 22(4), 888-898. doi:10.1109/tvlsi.2013.2252635
Aamir, Syed Ahmed, Angelova, Polina, and Wikner, J J. 2014. “A 1.2-V analog interface for a 300-MSps HD video digitizer in Core 65-nm CMOS”. IEEE Transactions on VLSI Systems 22 (4): 888-898.
Aamir, S. A., Angelova, P., and Wikner, J. J. (2014). A 1.2-V analog interface for a 300-MSps HD video digitizer in Core 65-nm CMOS. IEEE Transactions on VLSI Systems 22, 888-898.
Aamir, S.A., Angelova, P., & Wikner, J.J., 2014. A 1.2-V analog interface for a 300-MSps HD video digitizer in Core 65-nm CMOS. IEEE Transactions on VLSI Systems, 22(4), p 888-898.
S.A. Aamir, P. Angelova, and J.J. Wikner, “A 1.2-V analog interface for a 300-MSps HD video digitizer in Core 65-nm CMOS”, IEEE Transactions on VLSI Systems, vol. 22, 2014, pp. 888-898.
Aamir, S.A., Angelova, P., Wikner, J.J.: A 1.2-V analog interface for a 300-MSps HD video digitizer in Core 65-nm CMOS. IEEE Transactions on VLSI Systems. 22, 888-898 (2014).
Aamir, Syed Ahmed, Angelova, Polina, and Wikner, J J. “A 1.2-V analog interface for a 300-MSps HD video digitizer in Core 65-nm CMOS”. IEEE Transactions on VLSI Systems 22.4 (2014): 888-898.
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