A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity

Indiveri G, Chicca E, Douglas RJ (2006)
IEEE Transactions on Neural Networks 17(1): 211-221.

Zeitschriftenaufsatz | Veröffentlicht | Englisch
 
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Abstract / Bemerkung
We present a mixed-mode analog/digital VLSI device comprising an array of leaky integrate-and-fire (I&F) neurons, adaptive synapses with spike-timing dependent plasticity, and an asynchronous event based communication infrastructure that allows the user to (re)con figure networks of spiking neurons with arbitrary topologies. The asynchronous communication protocol used by the silicon neurons to transmit spikes (events) off-chip and the silicon synapses to receive spikes from the outside is based on the "address-event representation" (AER). We describe the analog circuits designed to implement the silicon neurons and synapses and present experimental data showing the neuron's response properties and the synapses characteristics, in response to AER input spike trains. Our results indicate that these circuits can be used in massively parallel VLSI networks of I&F neurons to simulate real-time complex spike-based learning algorithms.
Stichworte
spike-based learning; address-event representation (AER); neuromorphic circuits; spike-timing; analog VLSI; integrate-and-fire (I &; F) neurons; dependent plasticity (STDP)
Erscheinungsjahr
2006
Zeitschriftentitel
IEEE Transactions on Neural Networks
Band
17
Ausgabe
1
Seite(n)
211-221
ISSN
1045-9227
Page URI
https://pub.uni-bielefeld.de/record/2426586

Zitieren

Indiveri G, Chicca E, Douglas RJ. A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity. IEEE Transactions on Neural Networks. 2006;17(1):211-221.
Indiveri, G., Chicca, E., & Douglas, R. J. (2006). A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity. IEEE Transactions on Neural Networks, 17(1), 211-221. doi:10.1109/TNN.2005.860850
Indiveri, G., Chicca, E., and Douglas, R. J. (2006). A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity. IEEE Transactions on Neural Networks 17, 211-221.
Indiveri, G., Chicca, E., & Douglas, R.J., 2006. A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity. IEEE Transactions on Neural Networks, 17(1), p 211-221.
G. Indiveri, E. Chicca, and R.J. Douglas, “A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity”, IEEE Transactions on Neural Networks, vol. 17, 2006, pp. 211-221.
Indiveri, G., Chicca, E., Douglas, R.J.: A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity. IEEE Transactions on Neural Networks. 17, 211-221 (2006).
Indiveri, G., Chicca, Elisabetta, and Douglas, R. J. “A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity”. IEEE Transactions on Neural Networks 17.1 (2006): 211-221.
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2019-09-06T08:57:58Z
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