A multi-chip pulse-based neuromorphic infrastructure and its application to a model of orientation selectivity
Chicca E, Whatley AM, Lichtsteiner P, Dante V, Delbruck T, Del Giudice P, Douglas RJ, Indiveri G (2007)
IEEE-Transactions on Circuits and Systems I: Regular Papers 54(5): 981-993.
Zeitschriftenaufsatz
| Veröffentlicht | Englisch
Autor*in
Chicca, ElisabettaUniBi ;
Whatley, A. M.;
Lichtsteiner, P.;
Dante, V.;
Delbruck, T.;
Del Giudice, P.;
Douglas, R. J.;
Indiveri, G.
Einrichtung
Abstract / Bemerkung
The growing interest in pulse-mode processing by neural networks is encouraging the development of hardware implementations of massively parallel networks of integrate-and-fire neurons distributed over multiple chips. Address-event representation (AER) has long been considered a convenient transmission protocol for spike based neuromorphic devices. One missing, long-needed feature of AER-based systems is the ability to acquire data from complex neuromorphic systems and to stimulate them using suitable data. We have implemented a general-purpose solution in the form of a peripheral component interconnect (PCI) board (the PCI-AER board) supported by software. We describe the main characteristics of the PCI-AER board, and of the related supporting software. To show the functionality of the PCI-AER infrastructure we demonstrate a reconfigurable multichip neuromorphic system for feature selectivity which models orientation tuning properties of cortical neurons.
Stichworte
asynchronous;
address event representation (AER);
winner take all (WTA);
neural chips;
orientation tuning;
cooperative-competitive;
peripheral component interconnect (PCI)-AER;
VLSI;
neuromorphic;
neural networks
Erscheinungsjahr
2007
Zeitschriftentitel
IEEE-Transactions on Circuits and Systems I: Regular Papers
Band
54
Ausgabe
5
Seite(n)
981-993
ISSN
1057-7122
Page URI
https://pub.uni-bielefeld.de/record/2426576
Zitieren
Chicca E, Whatley AM, Lichtsteiner P, et al. A multi-chip pulse-based neuromorphic infrastructure and its application to a model of orientation selectivity. IEEE-Transactions on Circuits and Systems I: Regular Papers. 2007;54(5):981-993.
Chicca, E., Whatley, A. M., Lichtsteiner, P., Dante, V., Delbruck, T., Del Giudice, P., Douglas, R. J., et al. (2007). A multi-chip pulse-based neuromorphic infrastructure and its application to a model of orientation selectivity. IEEE-Transactions on Circuits and Systems I: Regular Papers, 54(5), 981-993. https://doi.org/10.1109/TCSI.2007.893509
Chicca, Elisabetta, Whatley, A. M., Lichtsteiner, P., Dante, V., Delbruck, T., Del Giudice, P., Douglas, R. J., and Indiveri, G. 2007. “A multi-chip pulse-based neuromorphic infrastructure and its application to a model of orientation selectivity”. IEEE-Transactions on Circuits and Systems I: Regular Papers 54 (5): 981-993.
Chicca, E., Whatley, A. M., Lichtsteiner, P., Dante, V., Delbruck, T., Del Giudice, P., Douglas, R. J., and Indiveri, G. (2007). A multi-chip pulse-based neuromorphic infrastructure and its application to a model of orientation selectivity. IEEE-Transactions on Circuits and Systems I: Regular Papers 54, 981-993.
Chicca, E., et al., 2007. A multi-chip pulse-based neuromorphic infrastructure and its application to a model of orientation selectivity. IEEE-Transactions on Circuits and Systems I: Regular Papers, 54(5), p 981-993.
E. Chicca, et al., “A multi-chip pulse-based neuromorphic infrastructure and its application to a model of orientation selectivity”, IEEE-Transactions on Circuits and Systems I: Regular Papers, vol. 54, 2007, pp. 981-993.
Chicca, E., Whatley, A.M., Lichtsteiner, P., Dante, V., Delbruck, T., Del Giudice, P., Douglas, R.J., Indiveri, G.: A multi-chip pulse-based neuromorphic infrastructure and its application to a model of orientation selectivity. IEEE-Transactions on Circuits and Systems I: Regular Papers. 54, 981-993 (2007).
Chicca, Elisabetta, Whatley, A. M., Lichtsteiner, P., Dante, V., Delbruck, T., Del Giudice, P., Douglas, R. J., and Indiveri, G. “A multi-chip pulse-based neuromorphic infrastructure and its application to a model of orientation selectivity”. IEEE-Transactions on Circuits and Systems I: Regular Papers 54.5 (2007): 981-993.
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