Design-space exploration of ultra-low power CMOS logic gates in a 28 nm FD-SOI technology

Vohrmann M, Geisler P, Jungeblut T, Ruckert U (2017)
In: 2017 European Conference on Circuit Theory and Design (ECCTD). IEEE.

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Vohrmann M, Geisler P, Jungeblut T, Ruckert U. Design-space exploration of ultra-low power CMOS logic gates in a 28 nm FD-SOI technology. In: 2017 European Conference on Circuit Theory and Design (ECCTD). IEEE; 2017.
Vohrmann, M., Geisler, P., Jungeblut, T., & Ruckert, U. (2017). Design-space exploration of ultra-low power CMOS logic gates in a 28 nm FD-SOI technology. 2017 European Conference on Circuit Theory and Design (ECCTD) IEEE. doi:10.1109/ecctd.2017.8093232
Vohrmann, M., Geisler, P., Jungeblut, T., and Ruckert, U. (2017). “Design-space exploration of ultra-low power CMOS logic gates in a 28 nm FD-SOI technology” in 2017 European Conference on Circuit Theory and Design (ECCTD) (IEEE).
Vohrmann, M., et al., 2017. Design-space exploration of ultra-low power CMOS logic gates in a 28 nm FD-SOI technology. In 2017 European Conference on Circuit Theory and Design (ECCTD). IEEE.
M. Vohrmann, et al., “Design-space exploration of ultra-low power CMOS logic gates in a 28 nm FD-SOI technology”, 2017 European Conference on Circuit Theory and Design (ECCTD), IEEE, 2017.
Vohrmann, M., Geisler, P., Jungeblut, T., Ruckert, U.: Design-space exploration of ultra-low power CMOS logic gates in a 28 nm FD-SOI technology. 2017 European Conference on Circuit Theory and Design (ECCTD). IEEE (2017).
Vohrmann, Marten, Geisler, Philippe, Jungeblut, Thorsten, and Ruckert, Ulrich. “Design-space exploration of ultra-low power CMOS logic gates in a 28 nm FD-SOI technology”. 2017 European Conference on Circuit Theory and Design (ECCTD). IEEE, 2017.
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