System-Level Analysis of Network Interfaces for Hierarchical MPSoCs

Ax J, Sievers G, Flasskamp M, Kelly W, Jungeblut T, Porrmann M (2015)
In: Proceedings of the 8th International Workshop on Network on Chip Architectures (NoCArc). New York, NY, USA: ACM: 3-8.

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Conference Paper | Published | English
Abstract
Network Interfaces (NIs) are used in Multiprocessor System-on-Chips (MPSoCs) to connect CPUs to a packet switched Network-on-Chip. In this work we introduce a new NI architecture for our hierarchical CoreVA-MPSoC. The CoreVA-MPSoC targets streaming applications in embedded systems. The main contribution of this paper is a system-level analysis of different NI configurations, considering both software and hardware costs for NoC communication. Different configurations of the NI are compared using a benchmark suite of 10 streaming applications. The best performing NI configuration shows an average speedup of 20 for a CoreVA-MPSoC with 32 CPUs compared to a single CPU. Furthermore, we present physical implementation results using a 28 nm FD-SOI standard cell technology. A hierarchical MPSoC with 8 CPU clusters and 4 CPUs in each cluster running at 800 MHz requires an area of 4.56 mm².
Publishing Year
Conference
International Workshop on Network on Chip Architectures (NoCArc)
Location
Waikiki, Hawaii
Conference Date
2015-12-05
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Ax J, Sievers G, Flasskamp M, Kelly W, Jungeblut T, Porrmann M. System-Level Analysis of Network Interfaces for Hierarchical MPSoCs. In: Proceedings of the 8th International Workshop on Network on Chip Architectures (NoCArc). New York, NY, USA: ACM; 2015: 3-8.
Ax, J., Sievers, G., Flasskamp, M., Kelly, W., Jungeblut, T., & Porrmann, M. (2015). System-Level Analysis of Network Interfaces for Hierarchical MPSoCs. Proceedings of the 8th International Workshop on Network on Chip Architectures (NoCArc), 3-8.
Ax, J., Sievers, G., Flasskamp, M., Kelly, W., Jungeblut, T., and Porrmann, M. (2015). “System-Level Analysis of Network Interfaces for Hierarchical MPSoCs” in Proceedings of the 8th International Workshop on Network on Chip Architectures (NoCArc) (New York, NY, USA: ACM), 3-8.
Ax, J., et al., 2015. System-Level Analysis of Network Interfaces for Hierarchical MPSoCs. In Proceedings of the 8th International Workshop on Network on Chip Architectures (NoCArc). New York, NY, USA: ACM, pp. 3-8.
J. Ax, et al., “System-Level Analysis of Network Interfaces for Hierarchical MPSoCs”, Proceedings of the 8th International Workshop on Network on Chip Architectures (NoCArc), New York, NY, USA: ACM, 2015, pp.3-8.
Ax, J., Sievers, G., Flasskamp, M., Kelly, W., Jungeblut, T., Porrmann, M.: System-Level Analysis of Network Interfaces for Hierarchical MPSoCs. Proceedings of the 8th International Workshop on Network on Chip Architectures (NoCArc). p. 3-8. ACM, New York, NY, USA (2015).
Ax, Johannes, Sievers, Gregor, Flasskamp, Martin, Kelly, Wayne, Jungeblut, Thorsten, and Porrmann, Mario. “System-Level Analysis of Network Interfaces for Hierarchical MPSoCs”. Proceedings of the 8th International Workshop on Network on Chip Architectures (NoCArc). New York, NY, USA: ACM, 2015. 3-8.
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