Frequency Compensation of High-Speed, Low-Voltage CMOS Multistage Amplifiers

Aamir SA, Harikumar P, Wikner JJ (2013)
In: 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013). Piscataway, NJ: IEEE: 381-384.

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Konferenzbeitrag | Veröffentlicht | Englisch
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Abstract / Bemerkung
This paper presents the frequency compensation of high-speed, low-voltage multistage amplifiers. Two frequency compensation techniques, the Nested Miller Compensation with Nulling Resistors (NMCNR) and Reversed Nested Indirect Compensation (RNIC), are discussed and employed on two multistage amplifier architectures. A four-stage pseudo-differential amplifier with CMFF and CMFB is designed in a 1.2 V, 65-nm CMOS process. With NMCNR, it achieves a phase margin (PM) of 59° with a DC gain of 75 dB and unity-gain frequency (fug) of 712 MHz. With RNIC, the same four-stage amplifier achieves a phase margin of 84°, DC gain of 76 dB and fug of 2 GHz. Further, a three-stage single-ended amplifier is designed in a 1.1-V, 40-nm CMOS process. The three-stage OTA with RNIC achieves PM of 81°, DC gain of 80 dB and fug of 770 MHz. The same OTA achieves PM of 59° with NMCNR, while maintaining a DC gain of 75 dB and fug of 262 MHz. Pole-splitting, to achieve increased stability, is illustrated for both compensation schemes. Simulations illustrate that the RNIC scheme achieves much higher PM and fug for lower values of compensation capacitance compared to NMCNR, despite the growing number of low voltage amplifier stages.
Erscheinungsjahr
Titel des Konferenzbandes
2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)
Seite
381-384
Konferenz
International Symposium on Circuits and Systems (ISCAS)
Konferenzort
Beijing, China
Konferenzdatum
2013-05-19 – 2013-05-23
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Aamir SA, Harikumar P, Wikner JJ. Frequency Compensation of High-Speed, Low-Voltage CMOS Multistage Amplifiers. In: 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013). Piscataway, NJ: IEEE; 2013: 381-384.
Aamir, S. A., Harikumar, P., & Wikner, J. J. (2013). Frequency Compensation of High-Speed, Low-Voltage CMOS Multistage Amplifiers. 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 381-384. Piscataway, NJ: IEEE. doi:10.1109/iscas.2013.6571860
Aamir, S. A., Harikumar, P., and Wikner, J. J. (2013). “Frequency Compensation of High-Speed, Low-Voltage CMOS Multistage Amplifiers” in 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013) (Piscataway, NJ: IEEE), 381-384.
Aamir, S.A., Harikumar, P., & Wikner, J.J., 2013. Frequency Compensation of High-Speed, Low-Voltage CMOS Multistage Amplifiers. In 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013). Piscataway, NJ: IEEE, pp. 381-384.
S.A. Aamir, P. Harikumar, and J.J. Wikner, “Frequency Compensation of High-Speed, Low-Voltage CMOS Multistage Amplifiers”, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), Piscataway, NJ: IEEE, 2013, pp.381-384.
Aamir, S.A., Harikumar, P., Wikner, J.J.: Frequency Compensation of High-Speed, Low-Voltage CMOS Multistage Amplifiers. 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013). p. 381-384. IEEE, Piscataway, NJ (2013).
Aamir, Syed Ahmed, Harikumar, Prakash, and Wikner, Jacob J. “Frequency Compensation of High-Speed, Low-Voltage CMOS Multistage Amplifiers”. 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013). Piscataway, NJ: IEEE, 2013. 381-384.
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