Design Flow for a Fault-Tolerant Reconfigurable Multi-FPGA Architecture for Space Applications

Köster M, Hagemeyer J, Margaglia F, Porrmann M, Dittmann F, Ditze M, Sterpone L, Harris J, Ilstad J (2011)
In: DATE 2011 Workshop on Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing. .

Conference Paper | Published | English

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Abstract
Sensor technology continues to improve at the price of increased data rates, which require being processed. In the space domain, the available bandwidth for effectively transferring the data to the base station is limited, such that there is a need for a high-performance data processing unit on board of the spacecraft. This work targets the development of a scalable high-performance payload data processing system based on dynamically reconfigurable FPGAs. The system, which is called Dynamically Reconfigurable Processing Module (DRPM), enables a multitude of high performance data processing applications to be supported by the same hardware in space. While reconfigurable hardware offers higher performances than traditional DSP-based solutions, it also supports the same flexibility to modify the functionality at run-time.
Publishing Year
Location
Grenoble, France
Conference Date
March 18 - 21
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Köster M, Hagemeyer J, Margaglia F, et al. Design Flow for a Fault-Tolerant Reconfigurable Multi-FPGA Architecture for Space Applications. In: DATE 2011 Workshop on Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing. 2011.
Köster, M., Hagemeyer, J., Margaglia, F., Porrmann, M., Dittmann, F., Ditze, M., Sterpone, L., et al. (2011). Design Flow for a Fault-Tolerant Reconfigurable Multi-FPGA Architecture for Space Applications. DATE 2011 Workshop on Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing.
Köster, M., Hagemeyer, J., Margaglia, F., Porrmann, M., Dittmann, F., Ditze, M., Sterpone, L., Harris, J., and Ilstad, J. (2011). “Design Flow for a Fault-Tolerant Reconfigurable Multi-FPGA Architecture for Space Applications” in DATE 2011 Workshop on Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing.
Köster, M., et al., 2011. Design Flow for a Fault-Tolerant Reconfigurable Multi-FPGA Architecture for Space Applications. In DATE 2011 Workshop on Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing.
M. Köster, et al., “Design Flow for a Fault-Tolerant Reconfigurable Multi-FPGA Architecture for Space Applications”, DATE 2011 Workshop on Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing, 2011.
Köster, M., Hagemeyer, J., Margaglia, F., Porrmann, M., Dittmann, F., Ditze, M., Sterpone, L., Harris, J., Ilstad, J.: Design Flow for a Fault-Tolerant Reconfigurable Multi-FPGA Architecture for Space Applications. DATE 2011 Workshop on Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing. (2011).
Köster, Markus, Hagemeyer, Jens, Margaglia, Fabio, Porrmann, Mario, Dittmann, Florian, Ditze, Michael, Sterpone, Luca, Harris, Julian, and Ilstad, Jorgen. “Design Flow for a Fault-Tolerant Reconfigurable Multi-FPGA Architecture for Space Applications”. DATE 2011 Workshop on Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing. 2011.
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