Evaluation of on-chip interfaces for dynamically reconfigurable coprocessors

Griese B, Kettelhoit B, Porrmann M (2006)
In: Proceedings of the 5th International Symposium on Parallel Computing in Electrical Engineering. 214-219.

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Konferenzbeitrag | Veröffentlicht | Englisch
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Abstract / Bemerkung
Dynamically reconfigurable FPGAs are well known to combine the flexibility of software with the performance of application specific hardware. As such they can be used as powerful but still flexible coprocessors in embedded processor systems. In this paper we analyze different variants for interfacing reconfigurable hardware from an embedded processor. We describe three different on-chip buses and evaluate their usability for dynamically reconfigurable systems. In addition, we analyze the communication latencies and the speed-up factor of a hardware accelerator for floating point operations for a total of eight different coupling variants
Erscheinungsjahr
Titel des Konferenzbandes
Proceedings of the 5th International Symposium on Parallel Computing in Electrical Engineering
Seite
214-219
Konferenzort
Bialystok, Poland
Konferenzdatum
September 13 - 17
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Griese B, Kettelhoit B, Porrmann M. Evaluation of on-chip interfaces for dynamically reconfigurable coprocessors. In: Proceedings of the 5th International Symposium on Parallel Computing in Electrical Engineering. 2006: 214-219.
Griese, B., Kettelhoit, B., & Porrmann, M. (2006). Evaluation of on-chip interfaces for dynamically reconfigurable coprocessors. Proceedings of the 5th International Symposium on Parallel Computing in Electrical Engineering, 214-219. doi:10.1109/PARELEC.2006.36
Griese, B., Kettelhoit, B., and Porrmann, M. (2006). “Evaluation of on-chip interfaces for dynamically reconfigurable coprocessors” in Proceedings of the 5th International Symposium on Parallel Computing in Electrical Engineering 214-219.
Griese, B., Kettelhoit, B., & Porrmann, M., 2006. Evaluation of on-chip interfaces for dynamically reconfigurable coprocessors. In Proceedings of the 5th International Symposium on Parallel Computing in Electrical Engineering. pp. 214-219.
B. Griese, B. Kettelhoit, and M. Porrmann, “Evaluation of on-chip interfaces for dynamically reconfigurable coprocessors”, Proceedings of the 5th International Symposium on Parallel Computing in Electrical Engineering, 2006, pp.214-219.
Griese, B., Kettelhoit, B., Porrmann, M.: Evaluation of on-chip interfaces for dynamically reconfigurable coprocessors. Proceedings of the 5th International Symposium on Parallel Computing in Electrical Engineering. p. 214-219. (2006).
Griese, Björn, Kettelhoit, Boris, and Porrmann, Mario. “Evaluation of on-chip interfaces for dynamically reconfigurable coprocessors”. Proceedings of the 5th International Symposium on Parallel Computing in Electrical Engineering. 2006. 214-219.

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