A Multiprocessor Cache for Massively Parallel SoC Architectures

Niemann J-C, Liß C, Porrmann M, Rückert U (2007)
In: ARCS'07: Architecture of Computing Systems. Zurich, Switzerland: 83-97.

Conference Paper | Published | English

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In this paper, we present an advanced multiprocessor cache architecture for chip multiprocessors (CMPs). It is designed for the scalable GigaNetIC CMP, which is based on massively parallel on-chip computing clusters. Our write-through multiprocessor cache is configurable in respect to the most relevant design options. It is supposed to be used in universal co-processors as well as in network processing units. For an early verification of the software and an early exploration of various hardware configurations, we have developed a SystemC-based simulation model for the complete chip multiprocessor. For detailed hardware-software co-verification, we use our FPGA-based rapid prototyping system RAPTOR2000 to emulate our architecture with near-ASIC performance. Finally, we demonstrate the performance gains for different application scenarios enabled by the usage of our multiprocessor cache.
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Niemann J-C, Liß C, Porrmann M, Rückert U. A Multiprocessor Cache for Massively Parallel SoC Architectures. In: ARCS'07: Architecture of Computing Systems. Zurich, Switzerland; 2007: 83-97.
Niemann, J. - C., Liß, C., Porrmann, M., & Rückert, U. (2007). A Multiprocessor Cache for Massively Parallel SoC Architectures. ARCS'07: Architecture of Computing Systems, 83-97.
Niemann, J. - C., Liß, C., Porrmann, M., and Rückert, U. (2007). “A Multiprocessor Cache for Massively Parallel SoC Architectures” in ARCS'07: Architecture of Computing Systems (Zurich, Switzerland), 83-97.
Niemann, J.-C., et al., 2007. A Multiprocessor Cache for Massively Parallel SoC Architectures. In ARCS'07: Architecture of Computing Systems. Zurich, Switzerland, pp. 83-97.
J.-C. Niemann, et al., “A Multiprocessor Cache for Massively Parallel SoC Architectures”, ARCS'07: Architecture of Computing Systems, Zurich, Switzerland: 2007, pp.83-97.
Niemann, J.-C., Liß, C., Porrmann, M., Rückert, U.: A Multiprocessor Cache for Massively Parallel SoC Architectures. ARCS'07: Architecture of Computing Systems. p. 83-97. Zurich, Switzerland (2007).
Niemann, Jörg-Christian, Liß, Christian, Porrmann, Mario, and Rückert, Ulrich. “A Multiprocessor Cache for Massively Parallel SoC Architectures”. ARCS'07: Architecture of Computing Systems. Zurich, Switzerland, 2007. 83-97.
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