A framework for design space exploration of resource efficient network processing on multiprocessor SoCs

Grünewald M, Niemann J-C, Porrmann M, Rückert U (2004)
In: Proceedings of the 3rd Workshop on Network Processors & Applications. Madrid, Spain: 87-101.

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Abstract
Hardware architectures based on a field of hardwareextended processors can provide flexible computing power for applications where parallelism can be exploited. For multiprocessors, the assignment of functionality to execution units can have a great impact on the performance. Additionally, finding the optimal mapping can be a timeconsuming task. We present a multiprocessor architecture along with a suitable design method that includes an automated solution to the mapping problem. Our hardware architecture employs a network-on-chip (NoC) to achieve a high degree of scalability for the application and for the system in respect to future integration technologies.We also show how to reduce the packet buffer requirements with a proper scheduling strategy and present first estimates for the resource consumption of an application targeted for mobile networking.
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Grünewald M, Niemann J-C, Porrmann M, Rückert U. A framework for design space exploration of resource efficient network processing on multiprocessor SoCs. In: Proceedings of the 3rd Workshop on Network Processors & Applications. Madrid, Spain; 2004: 87-101.
Grünewald, M., Niemann, J. - C., Porrmann, M., & Rückert, U. (2004). A framework for design space exploration of resource efficient network processing on multiprocessor SoCs. Proceedings of the 3rd Workshop on Network Processors & Applications, 87-101.
Grünewald, M., Niemann, J. - C., Porrmann, M., and Rückert, U. (2004). “A framework for design space exploration of resource efficient network processing on multiprocessor SoCs” in Proceedings of the 3rd Workshop on Network Processors & Applications (Madrid, Spain), 87-101.
Grünewald, M., et al., 2004. A framework for design space exploration of resource efficient network processing on multiprocessor SoCs. In Proceedings of the 3rd Workshop on Network Processors & Applications. Madrid, Spain, pp. 87-101.
M. Grünewald, et al., “A framework for design space exploration of resource efficient network processing on multiprocessor SoCs”, Proceedings of the 3rd Workshop on Network Processors & Applications, Madrid, Spain: 2004, pp.87-101.
Grünewald, M., Niemann, J.-C., Porrmann, M., Rückert, U.: A framework for design space exploration of resource efficient network processing on multiprocessor SoCs. Proceedings of the 3rd Workshop on Network Processors & Applications. p. 87-101. Madrid, Spain (2004).
Grünewald, Matthias, Niemann, Jörg-Christian, Porrmann, Mario, and Rückert, Ulrich. “A framework for design space exploration of resource efficient network processing on multiprocessor SoCs”. Proceedings of the 3rd Workshop on Network Processors & Applications. Madrid, Spain, 2004. 87-101.
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