Network application driven instruction set extensions for embedded processing clusters

Grunewald M, Le DK, Kastens U, Niemann J-C, Porrmann M, Rückert U, Slowik A, Thies M (2004)
In: Parallel Computing in Electrical Engineering, 2004. PARELEC 2004. International Conference on. 209-214.

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This paper addresses the design automation of instruction set extensions for application-specific processors with emphasis on network processing. Within this domain, increasing performance demands and the ongoing development of network protocols both call for flexible and performance-optimized processors. Our approach represents a holistic methodology for the extension and optimization of a processorýs instruction set. The starting point is a concise yet powerful processor abstraction, which is well suited to automatically generate the important parts of a compiler backend and cycle-accurate simulator so that domain-characteristic benchmarks can be analyzed for frequently occurring instruction pairs. These instruction pairs are promising candidates for the extension of the instruction set by means of super-instructions. Provided that a new super-instruction meets a given performance threshold, a fine-grained performance re-evaluation of the adapted processor design can be conducted instantly. With respect to the chosen domain-characteristic benchmark, the tool-chain pinpoints important characteristics such as execution performance, energy consumption, or chip area of the extended design. Using this holistic design methodology, we are able to judge a refinement of the processor rapidly.
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Grunewald M, Le DK, Kastens U, et al. Network application driven instruction set extensions for embedded processing clusters. In: Parallel Computing in Electrical Engineering, 2004. PARELEC 2004. International Conference on. 2004: 209-214.
Grunewald, M., Le, D. K., Kastens, U., Niemann, J. - C., Porrmann, M., Rückert, U., Slowik, A., et al. (2004). Network application driven instruction set extensions for embedded processing clusters. Parallel Computing in Electrical Engineering, 2004. PARELEC 2004. International Conference on, 209-214.
Grunewald, M., Le, D. K., Kastens, U., Niemann, J. - C., Porrmann, M., Rückert, U., Slowik, A., and Thies, M. (2004). “Network application driven instruction set extensions for embedded processing clusters” in Parallel Computing in Electrical Engineering, 2004. PARELEC 2004. International Conference on 209-214.
Grunewald, M., et al., 2004. Network application driven instruction set extensions for embedded processing clusters. In Parallel Computing in Electrical Engineering, 2004. PARELEC 2004. International Conference on. pp. 209-214.
M. Grunewald, et al., “Network application driven instruction set extensions for embedded processing clusters”, Parallel Computing in Electrical Engineering, 2004. PARELEC 2004. International Conference on, 2004, pp.209-214.
Grunewald, M., Le, D.K., Kastens, U., Niemann, J.-C., Porrmann, M., Rückert, U., Slowik, A., Thies, M.: Network application driven instruction set extensions for embedded processing clusters. Parallel Computing in Electrical Engineering, 2004. PARELEC 2004. International Conference on. p. 209-214. (2004).
Grunewald, M., Le, D.K., Kastens, U., Niemann, J.-C., Porrmann, Mario, Rückert, Ulrich, Slowik, A., and Thies, M. “Network application driven instruction set extensions for embedded processing clusters”. Parallel Computing in Electrical Engineering, 2004. PARELEC 2004. International Conference on. 2004. 209-214.
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