A mapping strategy for resource-efficient network processing on multiprocessor SoCs

Grunewald M, Niemann J-C, Porrmann M, Rückert U (2004)
In: Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings., 2. 758-763.

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Konferenzbeitrag | Veröffentlicht | Englisch
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Abstract / Bemerkung
Hardware architectures based on a field of hardwareextended processors can provide flexible computing power for applications where parallelism can be exploited. For multiprocessors, the assignment of functionality to execution units can have a great impact on the performance. Additionally, finding the optimal mapping can be a timeconsuming task. We present a multiprocessor architecture along with a suitable design method that includes an automated solution to the mapping problem. Our hardware architecture employs a network-on-chip (NoC) to achieve a high degree of scalability for the application and for the system in respect to future integration technologies.We also show how to reduce the packet buffer requirements with a proper scheduling strategy and present first estimates for the resource consumption of an application targeted for mobile networking.
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Titel des Konferenzbandes
Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings
Band
2
Seite
758-763
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Grunewald M, Niemann J-C, Porrmann M, Rückert U. A mapping strategy for resource-efficient network processing on multiprocessor SoCs. In: Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings. Vol 2. 2004: 758-763.
Grunewald, M., Niemann, J. - C., Porrmann, M., & Rückert, U. (2004). A mapping strategy for resource-efficient network processing on multiprocessor SoCs. Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings, 2, 758-763. doi:10.1109/DATE.2004.1268970
Grunewald, M., Niemann, J. - C., Porrmann, M., and Rückert, U. (2004). “A mapping strategy for resource-efficient network processing on multiprocessor SoCs” in Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings, vol. 2, 758-763.
Grunewald, M., et al., 2004. A mapping strategy for resource-efficient network processing on multiprocessor SoCs. In Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings. no.2 pp. 758-763.
M. Grunewald, et al., “A mapping strategy for resource-efficient network processing on multiprocessor SoCs”, Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings, vol. 2, 2004, pp.758-763.
Grunewald, M., Niemann, J.-C., Porrmann, M., Rückert, U.: A mapping strategy for resource-efficient network processing on multiprocessor SoCs. Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings. 2, p. 758-763. (2004).
Grunewald, M., Niemann, J.-C., Porrmann, Mario, and Rückert, Ulrich. “A mapping strategy for resource-efficient network processing on multiprocessor SoCs”. Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings. 2004.Vol. 2. 758-763.

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