Defragmentation Algorithms for Partially Reconfigurable Hardware

Köster M, Kalte H, Porrmann M, Rückert U (2007)
VLSI-SoC: From Systems to Silicon 240: 41-53.

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Zeitschriftenaufsatz | Veröffentlicht | Englisch
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Abstract / Bemerkung
Dynamic reconfiguration is a promising approach for resource efficient utilization of microelectronic systems. Standard platforms for partial dynamic reconfiguration are field-programmable gate arrays (FPGAs). Multiple hardware tasks can share the same FPGA resources over time, which increases the device utilization in comparison to non-reconfigurable systems. Although, similar resource management is already known in the area of operating systems, there is a requirement to adapt these concepts to the special needs of dynamically reconfigurable systems. Additionally, there is a lack of underlying mechanisms, e.g., to suspend hardware tasks and restart them at a different position within the FPGA. In this article we introduce a mechanism for task relocation that includes saving and restoring of state information of the task. Based on this approach we address the problem of defragmentation. We present defragmentation algorithms that minimize different types of costs. With the help of a detailed simulation model and a benchmark, we finally provide realistic simulation results and compare the different algorithms.
Erscheinungsjahr
Zeitschriftentitel
VLSI-SoC: From Systems to Silicon
Band
240
Seite
41-53
ISSN
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Köster M, Kalte H, Porrmann M, Rückert U. Defragmentation Algorithms for Partially Reconfigurable Hardware. VLSI-SoC: From Systems to Silicon. 2007;240:41-53.
Köster, M., Kalte, H., Porrmann, M., & Rückert, U. (2007). Defragmentation Algorithms for Partially Reconfigurable Hardware. VLSI-SoC: From Systems to Silicon, 240, 41-53. doi:10.1007/978-0-387-73661-7_4
Köster, M., Kalte, H., Porrmann, M., and Rückert, U. (2007). Defragmentation Algorithms for Partially Reconfigurable Hardware. VLSI-SoC: From Systems to Silicon 240, 41-53.
Köster, M., et al., 2007. Defragmentation Algorithms for Partially Reconfigurable Hardware. VLSI-SoC: From Systems to Silicon, 240, p 41-53.
M. Köster, et al., “Defragmentation Algorithms for Partially Reconfigurable Hardware”, VLSI-SoC: From Systems to Silicon, vol. 240, 2007, pp. 41-53.
Köster, M., Kalte, H., Porrmann, M., Rückert, U.: Defragmentation Algorithms for Partially Reconfigurable Hardware. VLSI-SoC: From Systems to Silicon. 240, 41-53 (2007).
Köster, M., Kalte, H., Porrmann, Mario, and Rückert, Ulrich. “Defragmentation Algorithms for Partially Reconfigurable Hardware”. VLSI-SoC: From Systems to Silicon 240 (2007): 41-53.

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