A System Approach for Partially Reconfigurable Architectures

Kalte H, Kettelhoit B, Koester M, Porrmann M, Rückert U (2005)
International Journal of Embedded Systems (IJES), Inderscience Publisher 1(3/4): 274-290.

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Zeitschriftenaufsatz | Veröffentlicht | Englisch
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Abstract / Bemerkung
The increasing logic density of current Field Programmable Gate Arrays (FPGA) enables the integration of whole systems on one programmable chip. Using concepts of partial dynamic reconfiguration allows the adaptation of complex systems to changing requirements at run-time. In this paper we present a realisable approach for dynamic system integration on Xilinx Virtex FPGAs. In contrast to existing approaches that consider fixed slots for module placement, our approach allows fine-grained placement of modules with variable width along a horizontal communication infrastructure. By simulation we show that the proposed 1D-approach outperforms 2D-approaches by means of the device utilisation and external fragmentation.
Erscheinungsjahr
Zeitschriftentitel
International Journal of Embedded Systems (IJES), Inderscience Publisher
Band
1
Zeitschriftennummer
3/4
Seite
274-290
ISSN
eISSN
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Kalte H, Kettelhoit B, Koester M, Porrmann M, Rückert U. A System Approach for Partially Reconfigurable Architectures. International Journal of Embedded Systems (IJES), Inderscience Publisher. 2005;1(3/4):274-290.
Kalte, H., Kettelhoit, B., Koester, M., Porrmann, M., & Rückert, U. (2005). A System Approach for Partially Reconfigurable Architectures. International Journal of Embedded Systems (IJES), Inderscience Publisher, 1(3/4), 274-290. doi:10.1504/IJES.2005.009956
Kalte, H., Kettelhoit, B., Koester, M., Porrmann, M., and Rückert, U. (2005). A System Approach for Partially Reconfigurable Architectures. International Journal of Embedded Systems (IJES), Inderscience Publisher 1, 274-290.
Kalte, H., et al., 2005. A System Approach for Partially Reconfigurable Architectures. International Journal of Embedded Systems (IJES), Inderscience Publisher, 1(3/4), p 274-290.
H. Kalte, et al., “A System Approach for Partially Reconfigurable Architectures”, International Journal of Embedded Systems (IJES), Inderscience Publisher, vol. 1, 2005, pp. 274-290.
Kalte, H., Kettelhoit, B., Koester, M., Porrmann, M., Rückert, U.: A System Approach for Partially Reconfigurable Architectures. International Journal of Embedded Systems (IJES), Inderscience Publisher. 1, 274-290 (2005).
Kalte, Heiko, Kettelhoit, Boris, Koester, Markus, Porrmann, Mario, and Rückert, Ulrich. “A System Approach for Partially Reconfigurable Architectures”. International Journal of Embedded Systems (IJES), Inderscience Publisher 1.3/4 (2005): 274-290.

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