A Chip for Selforganizing Feature Maps

Rüping S, Goser K, Rückert U (1995)
IEEE Micro 15(3): 57-59.

Journal Article | Published | English

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The use of self-organizing feature maps in real-time applications requires a high computational performance. Especially for embedded systems neural network chips are needed. In this paper a fabricated integrated circuit for self-organizing feature maps is presented. The architecture of this digital chip is based on the idea, that restrictions to the algorithm can simplify the implementation. Using the Manhattan Distance and a special treatment of the adaptation factor α decreases the necessary chip area, so that a high number of processor elements can be integrated on one chip. The effects of these restrictions on the function of the self-organizing feature map are discussed. The paper concludes with performance figures for a system architecture based on these chips
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Rüping S, Goser K, Rückert U. A Chip for Selforganizing Feature Maps. IEEE Micro. 1995;15(3):57-59.
Rüping, S., Goser, K., & Rückert, U. (1995). A Chip for Selforganizing Feature Maps. IEEE Micro, 15(3), 57-59.
Rüping, S., Goser, K., and Rückert, U. (1995). A Chip for Selforganizing Feature Maps. IEEE Micro 15, 57-59.
Rüping, S., Goser, K., & Rückert, U., 1995. A Chip for Selforganizing Feature Maps. IEEE Micro, 15(3), p 57-59.
S. Rüping, K. Goser, and U. Rückert, “A Chip for Selforganizing Feature Maps”, IEEE Micro, vol. 15, 1995, pp. 57-59.
Rüping, S., Goser, K., Rückert, U.: A Chip for Selforganizing Feature Maps. IEEE Micro. 15, 57-59 (1995).
Rüping, Stefan, Goser, Karl, and Rückert, Ulrich. “A Chip for Selforganizing Feature Maps”. IEEE Micro 15.3 (1995): 57-59.
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