Acceleratorboard for Neural Associative Memories

Rückert U, Funke A, Pintaske C (1993)
Neurocomputing 5: 39-49.

Journal Article | Published | English

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Describes a parallel and scalable architecture for rapid prototyping and fast emulation of neural associative memories (NAMs). The implementation is based on custom available components: RAMs and field programmable gate arrays (FPGAs). The use of FPGAs offers an alternative for parallel implementation of NAMs because the desired application can be realized very fast, and a flexible adjustment of the hardware to improved algorithms is possible without replacing chips. The developed accelerator board is designed as an ISA slot card for IBM-compatible PCs and can provide computational rates that are sufficient for the commercial implementation of a range of NAM applications. (PsycINFO Database Record (c) 2010 APA, all rights reserved)
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Rückert U, Funke A, Pintaske C. Acceleratorboard for Neural Associative Memories. Neurocomputing. 1993;5:39-49.
Rückert, U., Funke, A., & Pintaske, C. (1993). Acceleratorboard for Neural Associative Memories. Neurocomputing, 5, 39-49.
Rückert, U., Funke, A., and Pintaske, C. (1993). Acceleratorboard for Neural Associative Memories. Neurocomputing 5, 39-49.
Rückert, U., Funke, A., & Pintaske, C., 1993. Acceleratorboard for Neural Associative Memories. Neurocomputing, 5, p 39-49.
U. Rückert, A. Funke, and C. Pintaske, “Acceleratorboard for Neural Associative Memories”, Neurocomputing, vol. 5, 1993, pp. 39-49.
Rückert, U., Funke, A., Pintaske, C.: Acceleratorboard for Neural Associative Memories. Neurocomputing. 5, 39-49 (1993).
Rückert, Ulrich, Funke, A., and Pintaske, Christoph. “Acceleratorboard for Neural Associative Memories”. Neurocomputing 5 (1993): 39-49.
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